Abstract is missing.
- A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap Mixed-Signal FFE in 55nm BiCMOSMichiel Verplaetse, Hannes Ramon, N. Singh, Bart Moeneclaey, Peter Ossieur, Guy Torfs. 1-2 [doi]
- Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded SecurityWantong Li, Shanshi Huang, Xiaoyu Sun, Hongwu Jiang, Shimeng Yu. 1-2 [doi]
- A Low-Power Elliptic Curve Pairing Crypto-Processor for Secure Embedded Blockchain and Functional EncryptionUtsav Banerjee, Anantha P. Chandrakasan. 1-2 [doi]
- Quad Gate-Driver Controller with Start-Up and Shutdown for Cascaded Resonant Switched-Capacitor ConverterPourya Assem, Robert C. N. Pilawa-Podgurski. 1-2 [doi]
- nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time ArchitectureYanbo Zhang, Jin Zhang, Shubin Liu, Zhangming Zhu, Yan Zhu 0001, Chi-Hang Chan, R. P. Martins. 1-2 [doi]
- A 3.6dB NF, 23-39GHz Reflectionless RX with Absorptive Amplifier and Dual-Path Noise Cancelling LNA Supporting 64-QAM/256-QAM/1024-QAM for 5G NRZhixian Deng, Huizhen Jenny Qian, Xun Luo. 1-2 [doi]
- A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDRQiwen Liao, Miaofeng Li, Zhao Zhang 0004, Jian Liu, Nanjian Wu, Xi Xiao, Nan Qi. 1-2 [doi]
- A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correctionAhmed Elmallah, Junheng Zhu, Amr Khashaba, Karim M. Megawer, Ahmed Elkholy, Pavan Kumar Hanumolu. 1-2 [doi]
- A 28GHz Hybrid-Beamforming Transmitter Array Supporting Concurrent Dual Data Steams and Spatial Notch Steering for 5G MIMOYaolong Hu, Xiaohan Zhang, Taiyun Chi. 1-2 [doi]
- An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD QuantizerYi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, Nan Sun. 1-2 [doi]
- An 111pW Voltage Reference with a Diode-Leakage-Decoupling Replica for High-Temperature Miniature IoT SystemsYuyang Li, Inhee Lee. 1-2 [doi]
- A 50μW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature ExtractionTaewook Kang, Seungjong Lee, Mohammad Haghigat, Darren Abramson, Michael P. Flynn. 1-2 [doi]
- A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOSAlessandro Garghetti, Andrea Leonardo Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino. 1-2 [doi]
- Multisite bio-stimulating implants magnetoelectrically powered and individually programmed by a single transmitterZhanghao Yu, Joshua C. Chen, Yan He, Fatima T. Alrashdan, Benjamin W. Avants, Amanda Singer, Jacob T. Robinson, Kaiyuan Yang. 1-2 [doi]
- A 128x128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning ApplicationRezwan A. Rasul, Mike Shuo-Wei Chen. 1-2 [doi]
- Envelope-Tracking Supply Modulator with Trellis Search-Based Switching and 160MHz CapabilityWeiyu Leng, Asad A. Abidi, Sraavan R. Mundlapudi, Hooman Darabi, Debopriyo Chowdhury, Ali Afsahi, Sida Li. 1-2 [doi]
- A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific SimulationsChengshuo Yu, Yuqi Su, Jaeho Lee, Kevin T. C. Chai, Bongjin Kim. 1-2 [doi]
- 2 in-Memory Analog Matrix-Vector-Multiplier for DNN AccelerationIoannis A. Papistas, Stefan Cosemans, Bram Rooseleer, Jonas Doevenspeck, M.-H. Na, Arindam Mallik, Peter Debacker, Diederik Verkest. 1-2 [doi]
- A Dual-Mode 24-32 GHz 4-Element Phased-Array Transceiver Front-End with SSA Beamformer for Autonomous Agile Unknown Signal Tracking and Blocker Rejection within <0.1 us and 21.3%/15% Transmitter Peak/OP1dB PAEWei Zhu, Jiawen Wang, Ruitao Wang, Yan Wang. 1-2 [doi]
- CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic ApplicationsRakshith Saligram, Suman Datta, Arijit Raychowdhury. 1-2 [doi]
- Transceivers for 6G Wireless Communications: Challenges and Design SolutionsPayam Heydari. 1-8 [doi]
- A 1GS/s 82dB Peak-SFDR 12b Single-Channel Pipe-SAR ADC with Harmonic-Injecting Cross-Coupled-Pair and Fast N-replica Bootstrap Switch Achieving 7.5fj/conv-stepLiang Fang, Tao Fu, Xianshan Wen, Ping Gui. 1-2 [doi]
- A second-order temperature compensated 1μW/MHz 100MHz RC oscillator with ±140ppm inaccuracy from -40°C to 95°CKyu-Sang Park, Amr Khashaba, Ahmed Abdelrahman, Yongxin Li, Tianyu Wang 0006, Ruhao Xia, Nilanjan Pal, Pavan Kumar Hanumolu. 1-2 [doi]
- Dividerless Frequency Acquisition & Charge Pump Mismatch Compensation for Low-Power Millimeter-Wave Sub-Sampling PLLHao Wang 0079, Omeed Momeni. 1-8 [doi]
- 2 Duty-Cycled Resistor and Frequency-Locked-Loop-based Wheatstone Bridge Interface for Low Resistance Sensing SystemsJinyong Kim, Callen Votzke, Soumya Bose, Arun Natarajan, Matthew L. Johnston. 1-2 [doi]
- Fully Integrated Electronic-Photonic Sensor for Label-Free Refractive Index Sensing in Advanced Zero-Change CMOS-SOI ProcessChristos Adamopoulos, Sidney Buchbinder, Panagiotis G. Zarkos, Pavan Bhargava, Asmaysinh Gharia, Ali Ninkejad, Mekhail Anwar, Vladimir Stojanovic. 1-2 [doi]
- A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOSMarcel Runge, Dario Schmock, Tobias Kaiser, Friedel Gerfers. 1-2 [doi]
- A low-cost 0.98μW0.8V oversampled SAR ADC with pre-comparison and mismatch error shaping achieving 84.5dB SNDR and 103dB SFDRYuting Shen, Hanyue Li, Haoming Xin, Eugenio Cantatore, Pieter Harpe. 1-2 [doi]
- A13b-ENOB Third-Order Noise-Shaping SAR ADC using a Hybrid Error-Control StructureQihui Zhang, Jing Li, Zhong Zhang 0002, Kejun Wu, Ning Ning 0002, Qi Yu 0002. 1-2 [doi]
- A 5-100V Input Low-Profile Adaptive Delay Compensated Hysteretic LED Driver with Enhanced Current AccuracyOi Cheng, Jin Liu, Hoi Lee. 1-2 [doi]
- A Self-Resonant Boost Converter for Solar Energy Harvesting with 97% Tracking Efficiency, 80 mV Self-Startup and Ultra-Wide Range Source TrackingSeneke Chamith Chandrarathna, Jong-Wook Lee. 1-2 [doi]
- A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOSMarcel Runge, Julius Edler, Tobias Kaiser, Friedel Gerfers. 1-2 [doi]
- A 30GHz 4-way Series Doherty Digital Polar Transmitter Achieving 18% Drain Efficiency and -27.6dB EVM while Transmitting 300MHz 64-QAM OFDM SignalMohsen Mortazavi, Yiyu Shen, Dieuwert P. N. Mul, Leo C. N. de Vreede, Marco Spirito, Masoud Babaie. 1-2 [doi]
- A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOSArda Uran, Kerim Türe, Cosimo Aprile, Alix Trouillet, Florian Fallegger, Azita Emami, Stéphanie P. Lacour, Catherine Dehollain, Yusuf Leblebici, Volkan Cevher. 1-2 [doi]
- Electronics-photonics co-design for robust control of optical devices in dense integrated photonic circuitsFabio Toso, Francesco Zanetto, V. Grimaldi, A. Perino, Emanuele Guglielmi, Francesco Morichetti, Andrea Melloni, Giorgio Ferrari, Marco Sampietro. 1-8 [doi]
- A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOSHao Luo, Somnath Kundu, Chun Lee, Rinkle Jain, Sarah Shahraini, Eduardo Alban, Timo Huusari, Jason Mix, Nasser A. Kurd, Mohamed Abdel-moneum, Brent R. Carlton. 1-2 [doi]
- 56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS TechnologyTamer A. Ali 0001, Mohammed Abdullatif, Henry Park, E.-Hung Chen, Ramy Awad, Miguel Gandara. 1-6 [doi]
- MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADCHao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu 0001, Abhishek Mukherjee, Nan Sun, David Z. Pan. 1-2 [doi]
- A 40V Voltage-Compliance 12.75mA Maximum-Current Multipolar Neural Stimulator Using Time-Based Charge Balancing Technique Achieving 2mV PrecisionHaoran Pu, Ahmad Reza Danesh, Omid Malekzadeh-Arasteh, Won Joon Sohn, An H. Do, Zoran Nenadic, Payam Heydari. 1-2 [doi]
- 2 and 97.1% Peak EfficiencyAbdullah Abdulslam, Patrick P. Mercier. 1-2 [doi]
- An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal RecordingGeng Mu, Dawei Ye, Liangjian Lyu, Xiaobin Zhao, C.-J. Richard Shi. 1-2 [doi]
- A 2.7mW 45fsrms-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing ApplicationsJiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie. 1-2 [doi]
- A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOSMohamed A. Mokhtar, Ahmed Abdelaal, Markus Sporer, Joachim Becker, John G. Kauffman, Maurits Ortmanns. 1-2 [doi]
- A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and PerformanceRakshith Saligram, Divya Prasad, David Pietromonaco, Arijit Raychowdhury, Brian Cline. 1-2 [doi]
- 2Qiuzhen Xu, Kun Liao, Junzhong Yang, Pengda Qu, Feng Luo, Weibo Hu, Stephen VanDuyne, Zhiming Xiao. 1-2 [doi]
- Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power ManagementMeizhi Wang, Shanshan Xie, Ping Na Li, Aseem Sayal, Ge Li, Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni. 1-2 [doi]
- An In-Memory-Computing Charge-Domain Ternary CNN ClassifierXiangxing Yang, Keren Zhu 0001, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun. 1-2 [doi]
- A 24-Channel Neurostimulator IC with One-Shot Impedance-Adaptive Channel-Specific Charge BalancingFatemeh Eshaghi, Esmaeil Najafi Aghdam, Hossein Kassiri. 1-2 [doi]
- 3DIC Design Challenges, Early Solutions and Future RecommendationsVictoria Kolesov, Vivek Rajan, Ramune Nagisetty. 1-4 [doi]
- Integrated-Circuit Node for Time-Domain Near-infrared Diffuse Optical Tomography Imaging Arrays with On-chip Histogramming and Integrated VCSELsSajjad Moazeni, Kevin Renehan, Eric H. Pollmann, Kenneth L. Shepard. 1-2 [doi]
- A General-Regression-Neural-Network Based 5V-to-48V Three-Level Buck/Boost Power Converter with 40dB PSRR 90%-Efficiency for SSD Power Loss ProtectionChang Yang, Weizhong Chen, Yanli Fan, Ping Gui. 1-2 [doi]
- Coupled Inductors for Fast-Response High-Density Power Delivery: Discrete and IntegratedCharles R. Sullivan, Minjie Chen. 1-8 [doi]
- A Somatosensory Feedback System in 180nm CMOSHan Hao, Hangxing Liu, Jan Van der Spiegel, Firooz Aflatouni. 1-2 [doi]
- An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped ResonatorWei Deng 0001, Haikun Jia, Rui Wu, Shiyan Sun, Chenggang Li, Zhihua Wang, Baoyong Chi. 1-2 [doi]
- 2 in 55nm CMOSZhong Tang, Yun Fang, Xiao-peng Yu, Nianxiong Nick Tan, Zheng Shi, Pieter Harpe. 1-2 [doi]
- Nanoliter-Scale Autonomous Electronics: Advances, Challenges, and OpportunitiesAlyosha Christopher Molnar, SunWoo Lee, Alejandro J. Cortese, Paul L. McEuen, Sanaz Sadeghi, Shahaboddin Ghajari. 1-6 [doi]
- An Ultra-Compact 84.9-107GHz LNA with 4.9dB NF by Utilizing Coupled-line-based Gm-Boosting and Noise-Canceling Techniques in 65-nm CMOS TechnologyWei Zhu, Jiawen Wang, Ruitao Wang, Yan Wang. 1-2 [doi]
- A 16 pJ/bit 0.1-15Mbps Compressive Sensing IC with on-chip DWT Sparsifier for Audio SignalsK. Gaurav Kumar, Baibhab Chatterjee, Shreyas Sen. 1-2 [doi]
- Zero-Crossing-Based Bio-Engineered SensorQijun Liu, Arslan Riaz, Timur Zirtiloglu, Maria Eugenia Inda, Miguel Jimenez, Yong Lai, Christoph Steiger, Elizabeth Diamond, Giovanni Traverso, Timothy K. Lu, Anantha Chandrakasan, Phillip M. Nadeau, Rabia Tugce Yazicigil. 1-2 [doi]
- A 53GΩ@DC Input Impedance Multi-Channel Neural Recording Amplifier with 0.77 μVrms Input-Referred Noise for Deep Brain ImplantsHai Au Huynh, Milad Zamani, Margherita Ronchini, Hooman Farkhani, Farshad Moradi. 1-2 [doi]
- A 1.6 GS/s Spectrum Channelizer with PWM-LO Based Sub-band EqualizationKi-Yong Kim, Ranjit Gharpurey. 1-2 [doi]
- A 0.75-5V, 15.8 nA with 1.8 μs Delay Supply Voltage Supervisor using Adaptively Biased Comparator and Sample & Hold Technique for IoTAshutosh Chitnis, Rajat Chauhan, Divya Kaur, Qadeer Khan. 1-2 [doi]
- 3D-Split SRAM: Enabling Generational Gains in Advanced CMOSR. Mathur, M. Bhargava, H. Perry, Alberto Cestero, F. Frederick, S. Hung, C. Chao, D. Smith, D. Fisher, Norman Robson, X. Xu, Pranavi Chandupatla, R. Balachandran, S. Sinha, B. Cline, Jaydeep P. Kulkarni. 1-2 [doi]
- MemGen: An Open-Source Framework for Autonomous Generation of Memory MacrosSumanth Kamineni, Shourya Gupta, Benton H. Calhoun. 1-2 [doi]
- A 12-W 96.1%-Efficiency eFuse-Based Ultrafast Battery Charger Supporting Wireless and USB Power InputsYong Qu, Wei Shu, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang, Yue Li, Zixian Zheng, Joseph S. Chang. 1-2 [doi]
- A 94.1 dB DR 4.1 nW/Hz Bandwidth/Power Scalable DTDSM for IoT Sensing Applications Based on Swing-Enhanced Floating Inverter AmplifiersYiBo Zhao, Huajun Zhang, Yaopeng Hu, Yuanxin Bao, Le Ye, Wanyuan Qu, Menglian Zhao, Zhichao Tan. 1-2 [doi]
- A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization ProblemsYuqi Su, Junjie Mu, Hyunjoon Kim, Bongjin Kim. 1-2 [doi]
- 2/W High-PerformanceGuaranteed Efficiency in 55nm for Multi-Mode Pruning and Diverse Quantization Using Pattern-Kernel Encoding and Reconfigurable MAC UnitsZhanhong Tan, Sia Huat Tan, Jan-Henrik Lambrechts, Yannian Zhang, Yifu Wu, Kaisheng Ma. 1-2 [doi]
- A 256x256 6.3pJ/pixel-event Query-driven Dynamic Vision Sensor with Energy-conserving Row-parallel Event ScanningRajkumar Kubendran, Akshay Paul, Gert Cauwenberghs. 1-2 [doi]
- A 65nm Resonant Electro-Quasistatic 5-240uW Human Whole-Body Powering and 2.19uW Communication SoC with Automatic Maximum Resonant Power TrackingNirmoy Modak, Debayan Das, Mayukh Nath, Baibhab Chatterjee, K. Gaurav Kumar, Shovan Maity, Shreyas Sen. 1-2 [doi]
- Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel AttacksMeizhi Wang, Vishnuvardhan V. Iyer, Shanshan Xie, Ge Li, Sanu K. Mathew, Raghavan Kumar, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni. 1-2 [doi]
- A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon InterposerChester Liu, Jacob Botimer, Zhengya Zhang. 1-2 [doi]
- A Dual-Loop 4-Phase Switching LDO with Scalable Load Capability and Tunable Active Voltage Positioning for MicroprocessorsXiangyu Mao, Yan Lu, Rui P. Martins. 1-2 [doi]
- A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOSRajesh Inti, Mozhgan Mansuri, Joe Kennedy, Junyi Qiu, Chun-Ming Hsu, Jahnavi Sharma, Hao Li, Bryan Casper, James E. Jaussi. 1-2 [doi]
- A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop NeuromodulationArindam Mandal, Diego Peña, Rajesh Pamula 0001, Karam Khateeb, Logan Murphy, Azadeh Yazdan-Shahmorad, Steve I. Perlmutter, Forrest Pape, Jacques Christophe Rudell, Visvesh S. Sathe 0001. 1-2 [doi]
- Samsung Physically Unclonable Function (SAMPUF™) and its integration with Samsung Security SystemYongki Lee, Bohdan Karpinskyy, Yunhyeok Choi, Kyoung-Moon Ahn, YongSoo Kim, Jieun Park, Sumin Noh, Jisu Kang, Jonghoon Shin, Jaechul Park, Youngjin Chung, Jongshin Shin. 1-7 [doi]
- An Efficient Wireless Power and Data Transfer System with Current-Modulated Energy-Reuse Back Telemetry and Energy-Adaptive Dual-Input Voltage RegulationMinjae Kim, Hyun-Su Lee, Hyung-Min Lee. 1-2 [doi]
- A 94GHz Scalable 2 × 2 Phased-Array Receiver in SiGe BiCMOS for High Data-Rate CommunicationHuanbo Li, Jixin Chen, Debin Hou, Zekun Li, Rui Zhou, Wei Hong 0002. 1-2 [doi]
- An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer TechniquePingda Guan, Haikun Jia, Wei Deng 001, Zhihua Wang 0001, Baoyong Chi. 1-2 [doi]
- A Negative R-Assisted Amplifier on the Virtual Ground and Its ApplicationsYoungcheol Chae, Moon Hyung Jang, Changuk Lee, Sangwoo Lee, Seung-Woo Song. 1-6 [doi]
- Design Techniques of Integrated Power Management Circuits for Low Power Edge DevicesLi Xu 0006, Jeongsup Lee, Mehdi Saligane, David T. Blaauw, Dennis Sylvester. 1-4 [doi]
- An Energy Efficient Fully Integrated 20Gbps OOK Wireless Transmitter at 220GHzBahareh Hadidian, Farzad Khoeini, S. M. Hossein Naghavi, Andreia Cathelin, Ehsan Afshari. 1-2 [doi]
- A Digitally-Reconfigurable RC Frequency Generator using Impedance IQ-Balanced Frequency-Locked-Loop with Selectable Phase MixingBoyu Shen, Matthew L. Johnston. 1-2 [doi]
- A 26-32 GHz Dual-Polarization Receiver with Autonomous Polarization Alignment for Fast-Response Mm-Wave MIMO Links in Highly Dynamic Mobile EnvironmentsAmr Ahmed, Boce Lin, Hua Wang. 1-2 [doi]
- A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2, 2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency EnhancementAoyang Zhang, Mostafa Ayesh, Soumya Mahapatra, Mike Shuo-Wei Chen. 1-2 [doi]
- A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operationJong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury. 1-2 [doi]
- A 6μm-Precision Pulsed-Coherent Lidar with a 40-dB Tuning Range Inverter-Based Phase-Invariant PGALi-Yang Chen, Abhinav Kumar Vinod, James McMillan, Chee Wei Wong, Chih-Kong Ken Yang. 1-2 [doi]
- An Analog Low-Power Highly-Accurate Link-Adaptive Energy Storage Efficiency Maximizer for Resonant CM Wireless Power ReceiversMansour Taghadosi, Hossein Kassiri. 1-2 [doi]
- Prospects for High-Efficiency Silicon and lll-V Power Amplifiers and Transmitters in 100-300 GHz BandsJames F. Buckwalter, Mark J. W. Rodwell, Kang Ning 0002, Ahmed S. H. Ahmed, Andrea Arias-Purdue, Jeff Chien, Everett O'Malley, Eythan Lam. 1-7 [doi]