Chun-Ming Hsu - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 17 from 17

2022

2021

Introduction to the Special Section on High-Speed Wireline and Optical Communication Circuits and SystemsPing-Hsuan Hsieh, Chun-Ming Hsu, Yunzhi Dong. ojcands, 2:32-33, 2021. [doi]

A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOSRajesh Inti, Mozhgan Mansuri, Joe Kennedy, Junyi Qiu, Chun-Ming Hsu, Jahnavi Sharma, Hao Li, Bryan Casper, James E. Jaussi. cicc 2021: 1-2 [doi]

11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOSHao Li, Jahnavi Sharma, Chun-Ming Hsu, Ganesh Balamurugan, James E. Jaussi. isscc 2021: 190-192 [doi]

A 4×50 Gb/s All-Silicon Ring-based WDM Transceiver with CMOS ICHao Li, Zhe Xuan, Ranjeet Kumar, Meer Sakib, Jahnavi Sharma, Chun-Ming Hsu, Chaoxuan Ma, Haisheng Rong, Ganesh Balamurugan, James E. Jaussi. ecoc 2021: 1-3 [doi]

Silicon Photonic Micro-Ring Modulator-based 4 x 112 Gb/s O-band WDM Transmitter with Ring Photocurrent-based Thermal Control in 28nm CMOSJahnavi Sharma, Hao Li, Zhe Xuan, Ranjeet Kumar, Chun-Ming Hsu, Meer Sakib, Peicheng Liao, Haisheng Rong, James E. Jaussi, Ganesh Balamurugan. vlsic 2021: 1-2 [doi]

2019

56G/112G Link Foundations Standards, Link Budgets & ModelsGanesh Balamurugan, Ajay Balankutty, Chun-Ming Hsu. cicc 2019: 1-95 [doi]

2018

A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOSRajesh Inti, Mozhgan Mansuri, Joe Kennedy, Hariprasath Venkatram, Chun-Ming Hsu, Aaron Martin, James E. Jaussi, Bryan Casper. vlsic 2018: 151-152 [doi]

2014

2012

2011

2009

A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning LoopBelal Helal, Chun-Ming Hsu, Kerwin Johnson, Michael H. Perrott. jssc, 44(5):1391-1400, 2009. [doi]

2008

Techniques for high-performance digital frequency synthesis and phase controlChun-Ming Hsu. PhD thesis, Massachusetts Institute of Technology, Cambridge, MA, USA, 2008. [doi]

A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise CancellationChun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott. isscc 2008: 340-341 [doi]

A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise CancellationChun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott. jssc, 43(12):2776-2786, 2008. [doi]

Sign in or sign up to see more results.

runs on WebDSL