Michael H. Perrott - researchr alias

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Viewing Publication 1 - 34 from 34

2014

A clockless, multi-stable, CMOS analog circuitMohammad Alhawari, Michael H. Perrott. iscas 2014: 1764-1767 [doi]

A 0.5 V $< \hbox{4}\ \mu$W CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate SensorMohammad Alhawari, Nadya Albelooshi, Michael H. Perrott. jssc, 49(1):271-288, 2014. [doi]

2013

2012

A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stabilityMichael H. Perrott, Jim Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi. isscc 2012: 206-208 [doi]

2011

An Amplitude Resolution Improvement of an RF-DAC Employing Pulsewidth ModulationMin C. Park, Michael H. Perrott, Robert Bogdan Staszewski. tcas, 58-I(11):2590-2603, 2011. [doi]

2010

2009

A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning LoopBelal Helal, Chun-Ming Hsu, Kerwin Johnson, Michael H. Perrott. jssc, 44(5):1391-1400, 2009. [doi]

A Single-slope 80MS/s ADC using Two-Step Time-to-Digital ConversionMin C. Park, Michael H. Perrott. iscas 2009: 1125-1128 [doi]

A VCO-based Analog-to-digital Converter with Second-order Sigma-Delta Noise ShapingMin C. Park, Michael H. Perrott. iscas 2009: 3130-3133 [doi]

A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizerMin C. Park, Michael H. Perrott. isscc 2009: 170-171 [doi]

A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ΔΣ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 µm CMOSMatthew Park, Michael H. Perrott. jssc, 44(12):3344-3358, 2009. [doi]

A Multi-Path Gated Ring Oscillator TDC With First-Order Noise ShapingMatthew Z. Straayer, Michael H. Perrott. jssc, 44(4):1089-1098, 2009. [doi]

2008

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter PerformanceBelal Helal, Matthew Z. Straayer, Gu-Yeon Wei, Michael H. Perrott. jssc, 43(4):855-863, 2008. [doi]

A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise CancellationChun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott. isscc 2008: 340-341 [doi]

A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise CancellationChun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott. jssc, 43(12):2776-2786, 2008. [doi]

A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based QuantizerMatthew Z. Straayer, Michael H. Perrott. jssc, 43(4):805-814, 2008. [doi]

2006

A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 /spl mu/s offset compensationEthan Crain, Michael H. Perrott. jssc, 41(2):443-451, 2006. [doi]

A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noiseScott E. Meninger, Michael H. Perrott. jssc, 41(4):966-980, 2006. [doi]

A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop FilterMichael H. Perrott, Yunteng Huang, R. T. Baird, Bruno W. Garlepp, Ligang Zhang, J. P. Hein. isscc 2006: 1276-1285 [doi]

A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency AcquisitionMichael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore. jssc, 41(12):2930-2944, 2006. [doi]

2004

A numerical design approach for high speed, differential, resistor-loaded, CMOS amplifiersEthan Crain, Michael H. Perrott. iscas 2004: 508-511

2003

Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithmCharlotte Y. Lau, Michael H. Perrott. dac 2003: 526-531 [doi]

A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noiseS. E. Meninger, Michael H. Perrott. tcasII, 50(11):839-849, 2003. [doi]

Guest editorialMichael H. Perrott, Gu-Yeon Wei. tcasII, 50(11):773-774, 2003. [doi]

2002

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuitsMichael H. Perrott. dac 2002: 498-503 [doi]

Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL CircuitsMichael H. Perrott. dt, 19(4):74-83, 2002. [doi]

A modeling approach for /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers allowing straightforward noise analysisMichael H. Perrott, Mitchell D. Trott, Charles G. Sodini. jssc, 37(8):1028-1038, 2002. [doi]

1997

Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizersMichael H. Perrott. PhD thesis, Massachusetts Institute of Technology, Cambridge, MA, USA, 1997. [doi]

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulationMichael H. Perrott, Theodore L. Tewksbury III, Charles G. Sodini. jssc, 32(11):2048-2060, 1997. [doi]

1996

An efficient approach to ARMA modeling of biological systems with multiple inputs and delaysMichael H. Perrott, Richard J. Cohen. tbe, 43(1), 1996. [doi]

1993

A time domain approach for the fluctuation analysis of heart rate related to instantaneous lung volumeKazuo Yana, J. Philip Saul, Ronald D. Berger, Michael H. Perrott, Richard J. Cohen. tbe, 40(1):74-81, 1993. [doi]

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