Table of Contents

• Semiconductor Technologies Accelerate Our Future Vision: "ANSHIN Platform"Tsuneo Komatsuzaki, Yasushi Matsumoto, Yoshihiko Hiraoka, Yohei Kaieda, Hiroki Kunii. 1-4 [doi]
• A 7NM Double-Pumped 6R6W Register File for Machine Learning MemoryHoan Nguyen, Jihoon Jeong, Francois Atallah, Marc Jansen, Anthony Polomik, Daniel Yingling, Harsha Akkaraju, Brad Appel, Rahul Nadkarni, Keith A. Bowman. 1-2 [doi]
• An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOSV. Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh S. Sathe. 1-2 [doi]
• Hardware-Enabled Artificial IntelligenceWilliam J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson 0002, Larry R. Dennison. 3-6 [doi]
• A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET TechnologyMahmut E. Sinangil, Yen-Ting Lin, H. J. Liao, Jonathan Chang. 13-14 [doi]
• Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge SchemeWoong Choi, Jongsun Park 0001, Hoonki Kim, Changnam Park, Taejoong Song. 17-18 [doi]
• 12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAMMakoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka. 19-20 [doi]
• A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFETAmy Whitcombe, Borivoje Nikolic, Farhana Sheikh, Erkan Alpman, Ashoke Ravi. 23-24 [doi]
• An 113DB-Link-Budget Bluetooth-5 SoC with an 8dBm 22%-Efficiency TXTong Wang, Yosuke Ogasawara, Yuki Tuda, Tuan Thanh Ta, Masayoshi Oshiro, Jun Ihara, Tatsuhiko Maruyama, Toru Hashimoto, Akihide Sai, Takashi Tokairin. 25-26 [doi]
• Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOSYuta Toeda, Takumi Fujimaki, Mototsugu Hamada, Tadahiro Kuroda. 27-28 [doi]
• A Fast Triple-Interferer Sensor (Detector and Digital Encoder) with In-Situ Reference Frequency Acquisition at 2.7-to-3.7GHz in 0.13μM CMOSDongseok Shin, Kwang-Jin Koh. 29-30 [doi]
• Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected LayersZhe Yuan, Jinshan Yue, Huanrui Yang, Zhibo Wang, Jinyang Li 0002, Yixiong Yang, Qingwei Guo, Xueqing Li, Meng-Fan Chang, Huazhong Yang, Yongpan Liu. 33-34 [doi]
• A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and InferenceBruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan. 35-36 [doi]
• An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOSShouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei. 37-38 [doi]
• 2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOSMark Anders, Himanshu Kaul, Sanu Mathew, Vikram Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy. 39-40 [doi]
• New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI ApplicationsTaro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura. 41-42 [doi]
• A 112-GB/S PAM4 Transmitter in 16NM FinFETKee Hian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Arianne Roldan, Hongyuan Zhao, Nakul Narang, Siok-Wei Lim, Declan Carey, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Yohan Frans, Ken Chang. 45-46 [doi]
• A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFETJames Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang. 47-48 [doi]
• An Active Copper-Cable Supporting 56-Gbit/s PAM4 and 28-Gbit/s NRZ with Continuous Time Linear Equalizer IC for to-Meters Reach InterconnectionKoji Maeda, Takayasu Norimatsu, Kenji Kogo, Naohiro Kohmu, Kei Nishimura, Izumi Fukasaku. 49-50 [doi]
• A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOSHaram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Deog Kyoon Jeong. 51-52 [doi]
• A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOSThomas Toifl, Christian Menolfi, Matthias Brändli, Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Morf, Ilter Özkaya. 53-54 [doi]
• Memory Expansion Technology for Large-Scale Data Processing Using Software-Controlled SSDE. Yoshida, S. Kazama, S. Kuwamura, S. Gokita, T. Miyoshi, Y. Noguchi, Y. Honda. 59-60 [doi]
• An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOSPi-Feng Chiu, Christopher Celio, Krste Asanovic, David A. Patterson, Borivoje Nikolic. 61-62 [doi]
• An Adaptive Body-Biaslna SoC Using in Situ Slack Monitoring for Runtime Replica CalibrationMehdi Saligane, Jeongsup Lee, Qing Dong 0001, Makoto Yasuda, Kazuyuki Kumeno, Fumitaka Ohno, Satoru Miyoshi, Masaru Kawaminami, David T. Blaauw, Dennis Sylvester. 63-64 [doi]
• An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 ProcessorFahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, V. Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe. 65-66 [doi]
• A 252 × 144 SPAD Pixel Flash Lidar with 1728 Dual-Clock 48.8 PS TDCs, Integrated Histogramming and 14.9-to-1 Compression in 180NM CMOS TechnologyScott Lindner, Chao Zhang, Ivan Michel Antolovic, Martin Wolf, Edoardo Charbon. 69-70 [doi]
• A 220 M-Range Direct Time-of-Flight 688 × 384 CMOS Image Sensor with Sub-Photon Signal Extraction (SPSE) Pixels Using Vertical Avalanche Photo-Diodes and 6 KHz Light Pulse CountersShinzo Koyama, Motonori Ishii, Shigeru Saito, Masato Takemoto, Yugo Nose, Akito Inoue, Yusuke Sakata, Yuki Sugiura, Manabu Usuda, Tatsuya Kabe, Shigetaka Kasuga, Mitsuyoshi Mori, Yutaka Hirose, Akihiro Odagawa, Tsuyoshi Tanaka. 71-72 [doi]
• Multipurpose, Fully-Integrated 128×128 Event-Driven MD-SiPM with 512 16-Bit TDCs with 45 PS LSB and 20 NS GatingAugusto Carimatto, A. Ulku, Scott Lindner, E. D'Aillon, B. Rae, S. Pellegrini, Edoardo Charbon. 73-74 [doi]
• A Two-Tap NIR Lock-in Pixel CMOS Image Sensor with Background Light Cancelling Capability for Non-Contact Heart Rate DetectionChen Cao, Yuya Shirakawa, Leyi Tan, Min-Woong Seo, Keiichiro Kagawa, Keita Yasutomi, Tomohiko Kosugi, Satoshi Aoyama, Nobukazu Teranishi, Norimichi Tsumura, Shoji Kawahito. 75-76 [doi]
• Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access TimeYi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Jonathan Chang. 79-80 [doi]
• SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded MemoriesKevin Garello, Kevin Garello Yasin, S. Couet, Laurent Souriau, J. Swerts, S. Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, S. Kundu, Diana Tsvetanova, K. Croes, N. Jossart, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Fumemont, Pietro Gambardella, Gouri Sankar Kar. 81-82 [doi]
• High-Speed Voltage Control Spintronics Memory (VoCSM) Having Broad Design WindowsNaoharu Shimomura, Hiroaki Yoda, Tomoaki Inokuchi, Katsuhiko Koi, Hideyuki Sugiyama, Yushi Kato, Yuichi Ohsawa, Altansargai Buyandalai, Satoshi Shirotori, Soichi Oikawa, Mariko Shimizu, Mizue Ishikawa, Tiwari Ajay, Atsushi Kurobe. 83-84 [doi]
• Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT ApplicationsSupreet Jeloka, Zhehong Wang, Ruochen Xie, Sudhanshu Khanna, Steven Bartling, Dennis Sylvester, David T. Blaauw. 85-86 [doi]
• 14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive ProgrammingEric Hunt-Schroeder, Darren Anand, John Fifield, Mark Jacunski, Michael Roberge, Dale Pontius, Kevin Batson, Toshiaki Kirihata. 87-88 [doi]
• A 12-Bit 31.1UW 1MS/S SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4DB SFDR Using 256FF Sampling CapacitanceJunhua Shen, Akira Shikata, Anping Liu, Frederick Chalifoux. 91-92 [doi]
• A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based ComparatorZhaoming Ding, Xiong Zhou, Qiang Li. 93-94 [doi]
• A 2.3-MW, 950-MHz, 8-Bit Fully-Time-Based Subranging ADC Using Highly-Linear Dynamic VTCKenichi Ohhata. 95-96 [doi]
• A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DACHaiwen Chen, Xiong Zhot, Qiang Yu, Fan Zhang, Qiang Li. 97-98 [doi]
• A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFETBruno Vaz, Bob Verbruggen, Christophe Erdmann, Diarmuid Collins, John McGrath, Ali Boumaalif, Edward Cullen, Darragh Walsh, Alonso Morgado, Conrado Mesadri, Brian Long, Rajitha Pathepuram, Ronnie De La Torre, Alvin Manlapat, Georgios Karyotis, Dimitris Tsaliagos, Patrick Lynch, Peng Lim, Daire Breathnach, Brendan Farley. 99-100 [doi]
• A Single-Topology Continuously-Scalable-Conversion-Ratio Fully Integrated Switched-Capacitor DC-DC Converter with 0-to-2.22V Output and 93% Peak-EfficiencyNicolas Butzen, Michiel Steyaert. 103-104 [doi]
• New Methodology for Evaluating Minority Carrier Lifetime for Process AssessmentKuniyuki Kakushima, T. Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, Hitoshi Wakabayashi, Y. Numasawa, A. Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, H. Ohashi, Hiroshi Iwai. 105-106 [doi]
• A Quasi-Digital Ultra-Fast Capacitor-Less Low-Dropout Regulator Based on Comparator Control for x8 Current Spike of PCRAM SystemsSung-Won Choi, Yeunhee Huh, Sang-Hui Park, Kye-Seok Yoon, Jun-Suk Bang, Se-un Shin, Yong-Min Ju, Yu-Jin Yang, Junghyuk Yoon, Changyong Ahn, Taekseung Kim, Sung-Wan Hong, Gyu-Hyeong Cho. 107-108 [doi]
• 2 Fully-Integrated Digital LDO Based on Event-Driven Self-Trisuerina ControlDoyun Kim, Sung Kim, Mingoo Seok, Hyunju Ham, Jongwhan Kim. 109-110 [doi]
• A CMOS Molecular Clock Probing 231.061-GHz Rotational Line of OCS with Sub-PPB Long-Term Stability and 66-MW DC PowerCheng Wang 0009, Xiang Yi, Mina Kim, Yaqing Zhang, Ruonan Han 0001. 113-114 [doi]
• A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage AmplifierMasaya Miyahara, Yukiya Endo, Kenichi Okada, Akira Matsuzawa. 115-116 [doi]
• A 224 PW 260 PPM/°C Gate-Leakage-Based Timer for Ultra-Low Power Sensor Nodes with Second-Order Temperature Dependency CancellationJongyup Lim, Tae-Kwang Jang, Mehdi Saligane, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, David T. Blaauw, Dennis Sylvester. 117-118 [doi]
• A Sub-Leakage PW-Power HZ-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated SupplyOrazio Aiello, Paolo Crovetti, Massimo Alioto. 119-120 [doi]
• A 0.8V 82.9µW In-Ear BCI Controller System with 8.8 PEF EEG Instrumentational Amplifier and Wireless BAN TransceiverJaehyuk Lee, Kyoung-Rog Lee, Unsoo Ha, Ji-Hoon Kim, Kwonjoon Lee, Hoi-Jun Yoo. 123-124 [doi]
• A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing Optical Pulse ShapingAdam E. Mendrela, Sung Yun Park, Mihaly Voroslakos, Michael P. Flynn, Euisik Yoon. 125-126 [doi]
• Artifact-Tolerant Opamp-Less Delta-Modulated Bidirectional Neuro-InterfaceMohammad Reza Pazhouhandeh, Hossein Kassiri, Aly Shoukry, Iliya Wesspapir, Peter L. Carlen, Roman Genov. 127-128 [doi]
• A 400GΩ Input-Impedance, 220MVpp Linear-Input-Range, 2.8Vpp CM-Interference-Tolerant Active Electrode for Non-Contact Capacitively Coupled ECG AcquisitionMingyi Chen, Ivan Dario Castro, Qiuyang Lin, Tom Torfs, Filip Tavernier, Chris Van Hoof, Nick Van Helleputte. 129-130 [doi]
• Navion: A Fully Integrated Energy-Efficient Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano DronesAmr Suleiman, Zhengdong Zhang, Luca Carlone, Sertac Karaman, Vivienne Sze. 133-134 [doi]
• A1920 × 1080 25FPS, 2.4TOPS/W Unified Optical Flow and Depth 6D Vision Processor for Energy-Efficient, Low Power Autonomous NavigationZiyun Li, Jingcheng Wang, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim. 135-136 [doi]
• B-Face: 0.2 MW CNN-Based Face Recognition Processor with Face Alignment for Mobile User IdentificationSanghoon Kang, Jinmook Lee, Changhyeon Kim, Hoi-Jun Yoo. 137-138 [doi]
• A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOSShouyi Yin, Peng Ouyang, Shixuan Zheng, Dandan Song, Xiudong Li, Leibo Liu, Shaojun Wei. 139-140 [doi]
• A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data MovementHossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma. 141-142 [doi]
• A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFETJay Im, Stanley Chen, Dave Freitas, Adam Chou, Lei Zhou, Ian Zhuang, Tim Cronin, D. Mahashin, Winson Lin, Kok Lim Chan, Hongyuan Zhao, Kee Hian Tan, Ade Bekele, Didem Turker, Parag Upadhyaya, Yohan Frans, Ken Chang. 145-146 [doi]
• A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM ProcessJin-Hyeok Baek, Chang-Kyo Lee, Kiho Kim, Daesik Moon, Gil-Hoon Cha, Jin-Seok Heo, Min-Su Ahn, Dong-Ju Kim, Jae-Joon Song, Seokhong Kwon, Jongmin Kim, Kyung Soo Kim, Jinoh Ahn, Jeong-Sik Nam, Byungcheol Kim, Jeong-Hyeon Cho, Jeonghoon Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Ilgweon Kim, Hyuck-Joon Kwon, Young-Soo Sohn, Jung Hwan Choi, Kwang-Il Park, Seong-Jin Jang. 147-148 [doi]
• A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage SystemsYuta Tsubouchi, Daisuke Miyashita, Yuji Satoh, Takashi Toi, Fumihiko Tachibana, Makoto Morimoto, Junji Wadatsumi, Jun Deguchi. 149-150 [doi]
• A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOSRajesh Inti, Mozhgan Mansuri, Joe Kennedy, Hariprasath Venkatram, Chun-Ming Hsu, Aaron Martin, James E. Jaussi, Bryan Casper. 151-152 [doi]
• An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/BitEric Chang, Nathan Narevsky, Jaeduk Han, Elad Alon. 153-154 [doi]
• A 114-AF RMS- Resolution 46-NF/10-MΩ -Range Digital-Intensive Reconfigurable RC-to-Digital Converter with Parasitic-Insensitive Femto-Farad Baseline SensingArup K. George, Wooyoon Shim, Minkyu Je, Junghyup Lee. 157-158 [doi]
• A 117DB in-Band CMRR 98.5DB SNR Capacitance-to-Digital Converter for Sub-NM Displacement Sensing with an Electrically Floating TargetHui Jiang, Samira Amani, Johan G. Vogel, Saleh Heidary Shalmany, Stoyan N. Nihtianov. 159-160 [doi]
• A 181NW 970µG✓HZ Accelerometer Analog Front-End Employing Feedforward Noise Reduction TechniqueIppei Akita, Takayuki Okazawa, Yoshihiko Kurui, Akira Fujimoto, Takashi Asano. 161-162 [doi]
• A 2.69UW Dual Quantization-Based Capacitance-to-Digital Converter for Pressure, Humidity, and Acceleration Sensing in 0.18UM CMOSSujin Park, Geon-Hwi Lee, SeongHwan Cho. 163-164 [doi]
• 216-Channel CDMA-Like Period Modulation Capacitance-Tu-Diaital Converter with Reduced Data ThrouahputYuxuan Luo, Chun-Huat Heng. 165-166 [doi]
• An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote PlatformsSudhir Satpathy, Sanu Mathew, Vikram Suresh, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De. 169-170 [doi]
• A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAMKaiyuan Yang, Qing Dong 0001, Zhehong Wang, Yi-Chun Shih, Yu-Der Chih, Jonathan Chang, David T. Blaauw, Dennis Sylvester. 171-172 [doi]
• 4)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOSSudhir Satpathy, Vikram Suresh, Sanu Mathew, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy. 175-176 [doi]
• A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOSTing-Kuei Kuan, Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen 0001. 179-180 [doi]
• AMASS PLL: An Active-Mixer-Adopted Sub-Sampling PLL Achieving an FOM of -255.5DB and a Reference Spur of -66.6DBCDhon-Gue Lee, Patrick P. Mercier. 181-182 [doi]
• A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MWTsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski. 183-184 [doi]
• 153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock MultiplierSeojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi. 185-186 [doi]
• A Wireless Implantable Ultrasound Array Receiver for Thermoacoustic ImagingAhmed Sawaby, Max L. Wang, Ernest So, Jun-Chau Chien, Hao Nan, Butrus T. Khuri-Yakub, Amin Arbabian. 189-190 [doi]
• 316NW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature MeasurementXiao Wu 0002, Inhee Lee, Qing Dong 0001, Kaiyuan Yang, Dongkwun Kim, Jingcheng Wang, Yimai Peng, Yiqun Zhang 0002, Mehdi Saligane, Makoto Yasuda, Kazuyuki Kumeno, Fumitaka Ohno, Satoru Miyoshi, Masaru Kawaminami, Dennis Sylvester, David T. Blaauw. 191-192 [doi]
• Self-Regulated Wireless Power and Simultaneous 5MB/S Reverse Data over One Pair of CoilsJiacheng Pan, Asad A. Abidi, Wenlong Jiang, Dejan Rozgic, Dejan Markovic. 193-194 [doi]
• A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge NodesSuhwan Kim, Vaibhav Vaidya, Christopher Schaef, Andrew Lines, Harish Krishnamurthy, Sheldon Weng, Xiaosen Liu, Dileep Kurian, Tanay Karnik, Krishnan Ravichandran, James Tschanz, Vivek De. 195-196 [doi]
• A 1.2V 68µW 98.2DB-DR Audio Continuous-Time Delta-Sigma ModulatorChangwook Lee, Moon Hyung Jang, Youngcheol Chae. 199-200 [doi]
• nd-Order Noise-Shaping SAR QuantizerJiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun. 201-202 [doi]
• A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ∑Δ ADC Based on the Pipelined-SAR StructureYan Song, Yan Zhu 0001, Chi-Hang Chan, Li Geng, Rui Paulo Martins. 203-204 [doi]
• A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDRTakato Katayama, Shiko Miyashita, Kazuki Sobue, Koichi Hamashita. 205-206 [doi]
• A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOSBiao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins. 207-208 [doi]
• Terahertz RF Front-End Employing Even-Order Subharmonic MOS Symmetric Varactor Mixers in 65-NM CMOS for Hydration Measurements at 560 GHzQian Zhong, Wooyeol Choi, K. O. Kenneth. 211-212 [doi]
• A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G Operation for Enhancing Power Back-off EfficiencyAoyang Zhang, Mike Shuo-Wei Chen. 213-214 [doi]
• A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOSNereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx. 215-216 [doi]
• A 16-GB/S 0-DB Power Back-Off 16-QAM Transmitter at 28 GHZ in 65-NM CMOSXiangyu Meng, Can Wang, Milad Kalantari, C. Patrick Yue. 217-218 [doi]
• A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoCChristophe Erdmann, Bob Verbruggen, Bruno Vaz, Roberto Pelliconi, John McGrath, Ryan Kinnerk, Ronnie De La Torre, John O'Dwyer, Patrick Lynch, Padraig Kelly, Peng Lim, Daire Breathnach, Brendan Farley. 219-220 [doi]
• A 95.3% Peak Efficiency, 135NA Quiescent Current Buck-Boost DC-DC Converter with Current-Slope-Based Mode ControlDanzhu Lu, Peng Liu, Suyi Yao, Langyuan Wang, Jie He. 223-224 [doi]
• A Hybrid Dual-Path Step-Down Converter with 96.2% Peak Efficiency Using a $250\text{m}$ μ Large-DCR InductorYeunhee Huh, Se-un Shin, Sung-Wan Hong, Young-Jin Woo, Yong-Min Ju, Sung-Won Choi, Gyu-Hyeong Cho. 225-226 [doi]
• A 92.8% Efficiency Adaptive-On/Off-Time Control 3-Level Buck Converter for Wide Conversion Ratio with Shared Charge Pump Intermediate Voltage RegulatorYuki Karasawa, Takanobu Fukuoka, Kousuke Miyaji. 227-228 [doi]
• An Ultra-low Quiescent Current 250NA Low Dropout Regulator for No-Load to 10MA Internet-of-Evervthing ApplicationsShao-Qi Chen, Chia-Ming Huang, Ke-Homg Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 229-230 [doi]
• A Fully Integrated 700MA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management UnitJun-Eun Park, Deog Kyoon Jeong. 231-232 [doi]
• A 1MW -101DB THD+N Class-AB High-Fidelity Headphone Driver in 65NM CMOSNandish Mehta, Johan H. Huijsing, Vladimir Stojanovic. 235-236 [doi]
• A 2.2 NEF Neural-Recording Amplifier Using Discrete-Time Parametric AmplificationTae-Kwang Jang, Jongyup Lim, Kyojin David Choo, Samuel Nason, Jeongsup Lee, Jeongsup Oh, Seokhyeon Jeong, Cynthia Chestek, Dennis Sylvester, David T. Blaauw. 237-238 [doi]
• 6.5µW 92.3DB-DR Biopotential-Recording Front-End with 360MVPP Linear Input RangeJun-Suk Bang, Hyuntak Jeon, Minkyu Je, Gyu-Hyeong Cho. 239-240 [doi]
• A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOSKomail M. H. Badami, Kushal Dakshina Murthy, Pieter Harpe, Marian Verhelst. 241-242 [doi]
• A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and ProcessingLaurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Edith Beigné, Fabrice Guellec, Thomas Dombek, L. Benaissa, E. Deschaseaux, M. Duranton, K. Benchehida, Mehdi Darouich, Maria Lepecq. 245-246 [doi]
• A 2PJ/Pixel/Direction MIMO Processing Based CMOS Image Sensor for Omnidirectional Local Binary Pattern Extraction and Edge DetectionXiaopeng Zhong, Qian Yu, Amine Bermak, Chi-Ying Tsui, May-Kay Law. 247-248 [doi]
• Room-Temperature Quantum Sensing in CMOS: On-Chip Detection of Electronic Spin States in Diamond Color Centers for MagnetometryMohamed I. Ibrahim, Christopher Foy, Donggyu Kim, Dirk R. Englund, Ruonan Han 0001. 249-250 [doi]
• 3 Sensor Node with Initial Charge Delay Circuit for Battery ProtectionInhee Lee, Gyouho Kim, Eunseong Moon, Seokhyeon Jeong, Dongkwun Kim, Jamie Phillips, David T. Blaauw. 251-252 [doi]
• A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOSGregory K. Chen, Raghavan Kumar, H. Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy. 255-256 [doi]
• 2 0.22NJ/Pixel DL-Assisted 4K Video Encoder LSI for Quality-of-Experience Over Smart-PhonesTsu-Ming Liu, Chang-Hung Tsai, Tung-Hsing Wu, Jia-Ying Lin, Li-Heng Chen, Han-Liang Chou, Chi-Cheng Ju. 257-258 [doi]
• A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure ControlShuo-An Huang, Kai-Chieh Chang, Horng-Huei Liou, Chia-Hsiang Yang. 259-260 [doi]
• A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological SignalsYu-Zhe Wang, Yao-Pin Wang, Yi-Chung Wu, Chia-Hsiang Yang. 261-262 [doi]
• PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning AcceleratorsKentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka. 263-264 [doi]
• A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFEPier Andrea Francese, Alessandro Cevrero, Ilter Özkaya, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Toifl. 267-268 [doi]
• An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOSKevin Zheng, Yohan Frans, Sai Lalith Ambatipudi, Santiago Asuncion, Hari Teja Reddy, Ken Chang, Boris Murmann. 269-270 [doi]
• A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter ToleranceLong Kong, Yikun Chang, Behzad Razavi. 271-272 [doi]
• A 40GB/S Optical NRZ Transmitter Based on Monolithic Microring Modulators in 45NM SOI CMOSSen Lin, Sajjad Moazeni, Vladimir Stojanovic. 273-274 [doi]
• A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth CalibrationLukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Pier Andrea Francese, Matthias Braendli, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl. 275-276 [doi]