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Zhuang

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Parag Upadhyaya

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Publications by 'Ian Zhuang'

Publications

Viewing Publication 1 - 4 from 4

2018

A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFETStanley Chen, Lei Zhou, Ian Zhuang, Jay Im, Didem Turkur Melek, Jinyung Namkoong, Mayank Raj, Jaewook Shin, Yohan Frans, Ken Chang. isscc 2018: 390-392 [doi]

A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFETJay Im, Stanley Chen, Dave Freitas, Adam Chou, Lei Zhou, Ian Zhuang, Tim Cronin, D. Mahashin, Winson Lin, Kok Lim Chan, Hongyuan Zhao, Kee Hian Tan, Ade Bekele, Didem Turker, Parag Upadhyaya, Yohan Frans, Ken Chang. vlsic 2018: 145-146 [doi]

2017

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFETJay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang. isscc 2017: 114-115 [doi]

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFETJay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang. jssc, 52(12):3486-3502, 2017. [doi]

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