Table of Contents

• Semiconductor innovation: Is the party over, or just getting started?Vincent Roche. 8-11 [doi]
• Brain-Inspired technologies: Towards chips that think?Barbara De Salvo. 12-18 [doi]
• Future mobility-enhanced society enabled by semiconductor technologyYukihiro Kato. 21-26 [doi]
• 50 Years of computer architecture: From the mainframe CPU to the domain-specific tpu and the open RISC-V instruction setDavid Patterson. 27-31 [doi]
• Session 2 overview: Processors: Digital architectures and systems subcommitteeThomas Burd, Muhammad Khellah, Byeong-Gyu Nam. 32-33 [doi]
• SkyLake-SP: A 14nm 28-Core xeon® processorSimon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang. 34-36 [doi]
• IBM z14™: 14nm microprocessor for the next-generation mainframeChristopher J. Berry, James D. Warnock, John Isakson, John Badar, Brian Bell, Frank Malgioglio, Guenter Mayer, Dina Hamid, Jesse Surprise, David Wolpert, Ofer Geva, Bill Huott, Leon J. Sigal, Sean M. Carey, Richard F. Rizzolo, Ricardo Nigaglioni, Mark Cichanowski, Dureseti Chidambarrao, Christian Jacobi, Anthony Saporito, Arthur O'neill, Robert Sonnelitter, Christian G. Zoellin, Michael H. Wood, José Neves. 36-38 [doi]
• An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOSPascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan 0002, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James Tschanz, Vivek De. 38-40 [doi]
• 'Zeppelin': An SoC for multichip architecturesNoah Beck, Sean White, Milam Paraschou, Samuel Naffziger. 40-42 [doi]
• An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applicationsUtsav Banerjee, Chiraag Juvekar, Andrew Wright, Arvind, Anantha P. Chandrakasan. 42-44 [doi]
• A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensingLongyang Lin, Saurabh Jain, Massimo Alioto. 44-46 [doi]
• A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOSTanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De. 46-48 [doi]
• Session 3 overview: Analog techniques: Analog subcommitteeYoungcheol Chae, Mahdi Kashmiri, Kofi A. A. Makinwa. 48-49 [doi]
• A quiet digitally assisted auto-zero-stabilized voltage buffer with 0.6pA input current and offsetThije Rooijers, Johan H. Huijsing, Kofi A. A. Makinwa. 50-52 [doi]
• A regulation-free sub-0.5V 16/24MHz crystal oscillator for energy-harvesting BLE radios with 14.2nJ startup energy and 31.8pW steady-state powerKa-Meng Lei, Pui-In Mak, Man Kay Law, Rui P. Martins. 52-54 [doi]
• A CMOS Dual-RC frequency reference with ±250ppm inaccuracy from -45°C to 85°CCagri Gurleyuk, Lorenzo Pedala, Fabio Sebastiano, Kofi A. A. Makinwa. 54-56 [doi]
• A 2×20W 0.0013% THD+N Class-D audio amplifier with consistent performance up to maximum power levelEric Cope, Julian Aschieri, Tony Lai, Franklin Zhao, Walter Grandfield, Michael Clifford, Pete Rathfelder, Qiyuan Liu, Siddartha Kavilipati, Aaron Vandergriff, Gerald Miaille. 56-58 [doi]
• A 0.0004% (-108dB) THD+N, 112dB-SNR, 3.15W fully differential Class-D audio amplifier with Gm noise cancellation and negative output-common-mode injection techniquesWen-Chieh Wang, Yu-Hsin Lin. 58-60 [doi]
• A 0.96mA quiescent current, 0.0032% THD+N, 1.45W Class-D audio amplifier with area-efficient PWM-residual-aliasing reductionShih-Hsiung Chien, Yi-Wen Chen, Tai-Haur Kuo. 60-62 [doi]
• th-order programmable analog FIR filter using split-CDAC coefficient multipliers for wideband analog signal processingShinwoong Park, Dongseok Shin, Kwang-Jin Koh, Sanjay Raman. 62-64 [doi]
• Session 4 overview: mm-Wave radios for 5G and beyond: Wireless subcommitteeChun-Huat Heng, David McLaurin, Stefano Pellerano. 64-65 [doi]
• A 60GHz 144-element phased-array transceiver with 51dBm maximum EIRP and ±60° beam steering for backhaul applicationTirdad Sowlati, Saikat Sarkar, Bevin G. Perumana, Wei Liat Chan, Bagher Afshar, Michael Boers, Donghyup Shin, Timothy Mercer, Wei-Hong Chen, Anna Papio Toda, Alfred Grau Besoli, Seunghwan Yoon, Sissy Kyriazidou, Phil Yang, Vipin Aggarwal, Nooshin Vakilian, Dmitriy Rozenblit, Masoud Kahrizi, Joy Zhang, Alan Wang, Padmanava Sen, David Murphy, Mohyee Mikhemar, Ali Sajjadi, Alireza Tarighat Mehrabani, Brima Ibrahim, Bo Pan, Kevin Juan, Shelley Xu, Claire Guan, Guy Geshvindman, Khim Low, Namik Kocaman, Hans Eberhart, Koji Kimura, Igor Elgorriaga, Vincent Roussel, Hongyu Xie, Leo Shi, Venkat Kodavati. 66-68 [doi]
• A 23-to-30GHz hybrid beamforming MIMO receiver array with closed-loop multistage front-end beamformers for full-FoV dynamic and autonomous unknown signal tracking and blocker rejectionMin-Yu Huang, Taiyun Chi, Fei Wang, Tso-Wei Li, Hua Wang. 68-70 [doi]
• A 28GHz Bulk-CMOS dual-polarization phased-array transceiver with 24 channels for 5G user and basestation equipmentJeremy D. Dunworth, A. Homayoun, B.-H. Ku, Y. C. Ou, K. Chakraborty, G. Liu, T. Segoria, Jongrit Lerdworatawee, J. W. Park, H. C. Park, H. Hedayati, D. Lu, P. Monat, K. Douglas, Vladimir Aparin. 70-72 [doi]
• A reconfigurable 28/37GHz hybrid-beamforming MIMO receiver with inter-band carrier aggregation and RF-domain LMS weight adaptationSusnata Mondai, Rahul Singh, Jeyanandh Paramesh. 72-74 [doi]
• A fully integrated scalable W-band phased-array module with integrated antennas, self-alignment and self-testShahriar Shahramian, Mike Holyoak, Amit Singh, Bahar Jalali Farahani, Yves Baeyens. 74-76 [doi]
• A 64GHz full-duplex transceiver front-end with an on-chip multifeed self-interference-canceling antenna and an all-passive canceler supporting 4Gb/s modulation in one antenna footprintTaiyun Chi, Jong Seok Park, Sensen Li, Hua Wang. 76-78 [doi]
• Session 5 overview: Image sensors: IMMD subcommitteeHayato Wakabayashi, Makoto Ikeda, Makoto Ikeda. 78-79 [doi]
• A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADCMasaki Sakakibara, Koji Ogawa, Shin Sakai, Yasuhisa Tochigi, Katsumi Honda, Hidekazu Kikuchi, Takuya Wada, Yasunobu Kamikubo, Tsukasa Miura, Masahiko Nakamizo, Naoki Jyo, Ryo Hayashibara, Yohei Furukawa, Shinya Miyata, Satoshi Yamamoto, Yoshiyuki Ota, Hirotsugu Takahashi, Tadayuki Taura, Yusuke Oike, Keiji Tatani, Takashi Nagano, Takayuki Ezaki, Teruo Hirayama. 80-82 [doi]
• --saturation-signal organic-photoconductive-film global-shutter CMOS image sensor with in-pixel noise cancellerKazuko Nishimura, Sanshiro Shishido, Yasuo Miyake, Masaaki Yanagida, Yoshiaki Satou, Makoto Shouho, Hidenari Kanehara, Ryota Sakaida, Yoshihiro Sato, Junji Hirase, Yuko Tomekawa, Yutaka Abe, Hiroshi Fujinaka, Yoshiyuki Matsunaga, Masashi Murakami, Mitsuru Harada, Yasunori Inoue. 82-84 [doi]
• A 1/2.8-inch 24Mpixel CMOS image sensor with 0.9μm unit pixels separated by full-depth deep-trench isolationYitae Kim, Wonchul Choi, Donghyuk Park, Heegeun Jeoung, Bumsuk Kim, Youngsun Oh, Sunghoon Oh, Byungjun Park, Euiyeol Kim, YunKi Lee, Taesub Jung, Yongwoon Kim, Sukki Yoon, Seokyong Hong, Jesuk Lee, Sangil Jung, Changrok Moon, Yongin Park, Duckhyung Lee, Duckhyun Chang. 84-86 [doi]
• A 1/4-inch 3.9Mpixel low-power event-driven back-illuminated stacked CMOS image sensorOichi Kumagai, Atsumi Niwa, Katsuhiko Hanzawa, Hidetaka Kato, Shinichiro Futami, Toshio Ohyama, Tsutomu Imoto, Masahiko Nakamizo, Hirotaka Murakami, Tatsuki Nishino, Anas Bostamam, Takahiro Iinuma, Naoki Kuzuya, Kensuke Hatsukawa, Frederick Brady, William Bidermann, Toshifumi Wakano, Takashi Nagano, Hayato Wakabayashi, Yoshikazu Nitta. 86-88 [doi]
• A 1.1μm-Pitch 13.5Mpixel 3D-stacked CMOS image sensor featuring 230fps full-high-definition and 514fps high-definition videos by reading 2 or 3 rows simultaneously using a column-switching matrixPo-Sheng Chou, Chin-Hao Chang, Manoj M. Mhala, Charles Chih-Min Liu, Calvin Yi-Ping Chao, Chiao-Yi Huang, Honyih Tu, Thomas Meng-Hsiu Wu, Shang-Fu Yeh, Seiji Takahashi, Yi-Min Huang. 88-90 [doi]
• A 33Mpixel CMOS imager with multi-functional 3-stage pipeline ADC for 480fps high-speed mode and 120fps low-noise modeToshio Yasue, Kohei Tomioka, Ryohei Funatsu, Tomohiro Nakamura, Takahiro Yamasaki, Hiroshi Shimamoto, Tomohiko Kosugi, Sung-Wook Jun, Takashi Watanabe, Masanori Nagase, Toshiaki Kitajima, Satoshi Aoyama, Shoji Kawahito. 90-92 [doi]
• A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation techniqueKentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiro Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto. 92-94 [doi]
• IMpixel 65nm BSI 320MHz demodulated TOF Image sensor with 3μm global shutter pixels and analog binningCyrus S. Bamji, Swati Mehta, Barry Thompson, Tamer A. Elkhatib, Stefan Wurster, Onur Can Akkaya, Andrew D. Payne, John P. Godbaz, Mike Fenton, Vijay Rajasekaran, Larry Prather, Satya Nagaraja, Vishali Mogallapu, Dane Snow, Rich McCauley, Mustansir Mukadam, Iskender Agi, Shaun McCarthy, Zhanping Xu, Travis Perry, William Qian, Vei-Han Chan, Prabhu Adepu, Gazi Ali, Muneeb Ahmed, Aditya Mukherjee, Sheethal Nayak, Dave Gampell, Sunil Acharya, Lou Kordus, Patrick O'Connor. 94-96 [doi]
• A 256×256 45/65nm 3D-stacked SPAD-based direct TOF image sensor for LiDAR applications with optical polar modulation for up to 18.6dB interference suppressionAugusto Ronchini Ximenes, Preethi Padmanabhan, Myung-Jae Lee, Yuichiro Yamashita, D. N. Yaung, Edoardo Charbon. 96-98 [doi]
• A 32×32-pixel time-resolved single-photon image sensor with 44.64μm pitch and 19.48% fill-factor with on-chip row/frame skipping features reaching 800kHz observation rate for quantum physics applicationsLeonardo Gasparini, Majid Zarghami, Hesong Xu, Luca Parmesan, Manuel Moreno Garcia, Manuel Unternahrer, Banz Bessire, Andre Stefanov, David Stoppa, Matteo Perenzoni. 98-100 [doi]
• Session 6 overview: Ultra-high-speed wireline: Wireline subcommitteeMounir Meghelli, Hyeon-Min Bae, Frank O'Mahony. 100-101 [doi]
• A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOSJihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Skyler Weaver, Kai Yu, Frank O'Mahony. 102-104 [doi]
• A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOSChristian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Alessandro Cevrero, Marcel A. Kossel, Lukas Kull, Danny Luu, Ilter Özkaya, Thomas Toifl. 104-106 [doi]
• A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate supportMohammad Sadegh Jalali, Mohammad Hossein Taghavi, Angus McLaren, Jennifer Pham, Kamran Farzan, Dominic DiClemente, Marcus van Ierssel, William Song, Saman Asgaran, Chris D. Holdenried, Saman Sadr. 106-108 [doi]
• A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFETParag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang. 108-110 [doi]
• A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFETLuke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone. 110-112 [doi]
• A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOSEmanuele Depaoli, Enrico Monaco, Giovanni Steffan, Marco Mazzini, Hongyang Zhang, Walter Audoglio, Oscar Belotti, Augusto Andrea Rossi, Guido Albasini, Massimo Pozzoni, Simone Erba, Andrea Mazzanti. 112-114 [doi]
• A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOSLiangxiao Tang, Weixin Gai, Linqi Shi, Xiao-xiang, Kai Sheng, Ai He. 114-116 [doi]
• Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommitteeYoungmin Shin, Phillip Restle, Edith Beigné. 116-117 [doi]
• 2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOMShiheng Yang, Jun Yin, Pui-In Mak, Rui P. Martins. 118-120 [doi]
• 2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technologyKangyeop Choo, Hyunik Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hyung Jong Ko. 120-122 [doi]
• A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDCMinseob Lee, Shinwoong Kim, Hwasuk Cho, Jahyun Koo, Kwang-Hee Choi, Jin Hyeok Choi, Byungsub Kim, Hong June Park, Jae-Yoon Sim. 122-124 [doi]
• A 55nm time-domain mixed-signal neuromorphic accelerator with stochastic synapses and embedded reinforcement learning for autonomous micro-robotsAnvesha Amaravati, Saad Bin Nasir, Sivaram Thangadurai, Insik Yoon, Arijit Raychowdhury. 124-126 [doi]
• An enhanced-security buck DC-DC converter with true-random-number-based pseudo hysteresis controller for internet-of-everything (IoE) DevicesWen-Hau Yang, Li-Cheng Chu, Shang-Hsien Yang, Yan-Jiun Lai, Shao-Qi Chen, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 126-128 [doi]
• A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDDNail Etkin Can Akkaya, Burak Erbagci, Ken Mai. 128-130 [doi]
• A PUF scheme using competing oxide rupture with bit error rate approaching zeroMeng-Yi Wu, Tsao-Hsin Yang, Lun-Chun Chen, Chi-Chang Lin, Hao-Chun Hu, Fang-Ying Su, Chih-Min Wang, James Po-Hao Huang, Hsin-Ming Chen, Chris Chun-Hung Lu, Evans Ching-Song Yang, Rick Shih-Jye Shen. 130-132 [doi]
• 2 leakage-based physically unclonable Function with Lossless Stabilization Through Remapping for IoT SecurityJongmin Lee, Donghyeon Lee, Yongmin Lee, Yoonmyung Lee. 132-134 [doi]
• Session 8 overview: Wireless power and harvesting: Power management subcommitteeYuan Gao, Zhiliang Hong, Axel Thomsen. 134-135 [doi]
• A 960pW Co-Integrated-Antenna Wireless Energy Harvester for WiFi Backchannel Wireless PoweringKamala Raghavan Sadagopan, Jian Kang, Yogesh Ramadass, Arun Natarajan. 136-138 [doi]
• A 70W and 90% GaN-based class-E wireless-power-transfer system with automatic-matching-point-search control for zero-voltage switching and zero-voltage-derivative switchingChe-Hao Yeh, Yen-Ting Lin, Chun-Chieh Kuo, Chao-Jen Huang, Cheng-Yu Xie, Shen-Fu Lu, Wen-Hau Yang, Ke-Horng Chen, Kuo-Chi Liu, Ying-Hsi Lin. 138-140 [doi]
• A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiencyFangyu Mao, Yan Lu 0002, Seng-Pan U., Rui P. Martins. 140-142 [doi]
• A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output PowerYu Wang 0046, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, C.-J. Richard Shi. 142-144 [doi]
• MISIMO: A multi-input single-inductor multi-output energy harvester employing event-driven MPPT control to achieve 89% peak efficiency and a 60, 000x dynamic range in 28nm FDSOISally Safwat Amin, Patrick P. Mercier. 144-146 [doi]
• A 4.5-to-16μW integrated triboelectric energy-harvesting system based on high-voltage dual-input buck converter with MPPT and 70V maximum input voltageInho Park, Junyoung Maeng, Dongju Lim, Minseob Shim, Junwon Jeong, Chulwoo Kim. 146-148 [doi]
• A piezoelectric energy-harvesting interface circuit with fully autonomous conjugate impedance matching, 156% extended bandwidth, and 0.38μW power consumptionYifeng Cai, Yiannos Manoli. 148-150 [doi]
• A 30nA quiescent 80nW-to-14mW power-range shock-optimized SECE-based piezoelectric harvesting interface with 420% harvested-energy improvementAnthony Quelen, Adrien Morel, Pierre Gasnier, Romain Grezaud, Stephane Monfray, Gaël Pillonnet. 150-152 [doi]
• A fully integrated split-electrode synchronized-switch-harvesting-on-capacitors (SE-SSHC) rectifier for piezoelectric energy harvesting with between 358% and 821% power-extraction enhancementSijun Du, Ashwin A. Seshia. 152-154 [doi]
• A 13.56MHz time-interleaved resonant-voltage-mode wireless-power receiver with isolated resonator and quasi-resonant boost converter for implantable systemsSe-un Shin, Minseong Choi, Seok-Tae Koh, Yu-Jin Yang, Seungchul Jung, Young-Hoon Sohn, Se-Hong Park, Yong-Min Ju, Youngsin Jo, Yeunhee Huh, Sung-Won Choi, Sang Joon Kim, Gyu-Hyeong Cho. 154-156 [doi]
• Session 9 overview: Wireless transceivers and techniques: Wireless subcommitteeAlan Wong, Xin He, Stefano Pellerano. 156-157 [doi]
• A multimode 76-to-81GHz automotive radar transceiver with autonomous monitoringBrian P. Ginsburg, Karthik Subburaj, Sreekiran Samala, Karthik Ramasubramanian, Jasbir Singh, Sumeer Bhatara, Sriram Murali, Dan Breen, Meysam Moallem, Krishnanshu Dandu, Saket Jalan, Neeraj P. Nayak, Rittu Sachdev, Indu Prathapan, Karan Bhatia, Tim Davis, Eunyoung Seok, Harikrishna Parthasarathy, Rohit Chatterjee, Venkatesh Srinivasan, Vito Giannini, Anil Kumar, Ross Kulak, Shankar Ram, Pankaj Gupta, Zahir Parkar, Sachin Bhardwaj, Y. C. Rakesh, K. A. Rajagopal, Arun Shrimali, Vijay Rentala. 158-160 [doi]
• A 253mW/channel 4TX/4RX pulsed chirping phased-array radar TRX in 65nm CMOS for X-band synthetic-aperture radar imagingLiheng Lou, Kai Tang, Bo Chen, Ting Guo, Yisheng Wang, Wensong Wang, Zhongyuan Fang, Zhe Liu, Yuanjin Zheng. 160-162 [doi]
• A highly reconfigurable 65nm CMOS RF-to-bits transceiver for full-band multicarrier TDD/FDD 2G/3G/4G/5G macro basestationsDavid J. McLaurin, Kevin G. Gard, Richard P. Schubert, Manish J. Manglani, Haiyang Zhu, David Alldred, Zhao Li, Steven R. Bal, Jianxun Fan, Oliver E. Gysel, Christopher M. Mayer, Tony Montalvo. 162-164 [doi]
• A 40Gb/s 6pJ/b RX baseband in 28nm CMOS for 60GHz polarization MIMOShinwon Kang, Chintan Thakkar, Nathan Narevsky, Kaushik Dasgupta, Saeid Daneshgar, James E. Jaussi, Bryan Casper. 164-166 [doi]
• A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMOSaeid Daneshgar, Kaushik Dasgupta, Chintan Thakkar, Anandaroop Chakrabarti, Shuhei Yamada, Debabani Choudhury, James E. Jaussi, Bryan Casper. 166-168 [doi]
• A 120Gb/s 16QAM CMOS millimeter-wave wireless transceiverKorkut Kaan Tokgoz, Shotaro Maki, Jian Pang, Noriaki Nagashima, Ibrahim Abdo, Seitaro Kawai, Takuya Fujimura, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa. 168-170 [doi]
• A broadband and deep-TX self-interference cancellation technique for full-duplex and frequency-domain-duplex transceiver applicationsKun-Da Chu, Mohamad Katanbaf, Tong Zhang, Chenxin Su, Jacques C. Rudell. 170-172 [doi]
• A 1.4-to-2.7GHz high-efficiency RF transmitter with an automatic 3FLO-suppression tracking-notch-filter mixer supporting HPUE in 14nm FinFET CMOSQing Liu, Dae Hyun Kwon, Quang-Diep Bui, Jeong-Hyun Choi, Jaehun Lee, Sanghyun Baek, Seungchan Heo, Thomas Byunghak Cho. 172-174 [doi]
• A high-efficiency 28GHz outphasing PA with 23dBm output power using a triaxial balun combinerBagher Rabet, James Buckwalter. 174-176 [doi]
• Session 10 overview: Sensor systems: IMMD subcommitteeMichael Kraft, Masayuki Miyamoto, Makoto Ikeda. 176-177 [doi]
• Chopped rate-to-digital FM gyroscope with 40ppm scale factor accuracy and 1.2dph biasBurak Eminoglu, Bernhard E. Boser. 178-180 [doi]
• Personal inertial navigation system employing MEMS wearable ground reaction sensor array and interface ASIC achieving a position accuracy of 5.5m over 3km walking distance without GPSQingbo Guo, William Deng, Ozkan Bebek, Murat Cenk Cavusoglu, Carlos H. Mastrangelo, Darrin J. Young. 180-182 [doi]
• Multi-way interactive capacitive touch system with palm rejection of active stylus for 86" touch screen panelsJae-Sung An, Sang-Hyun Han, Kyeong-Bin Park, Ju Eon Kim, Jae-Hun Ye, Seung Hwan Lee, Ji-Yong Jeong, Jung Soo Kim, Kwang-Hyun Baek, Ki-Seok Chung, Seong-Kwan Hong, Oh-Kyong Kwon. 182-184 [doi]
• A noise-immune stylus analog front-end using adjustable frequency modulation and linear-interpolating data reconstruction for both electrically coupled resonance and active stylusesKyung-Hoon Lee, Sang-Pil Nam, Jung-Ho Lee, Michael Choi, Hyung Jong Ko, San-Ho Byun, Jin-chul Lee, Yong-Hoon Lee, Yeong-Cheol Rhee, Yoon Kyung Choi, Byunghoon Kang, Changbyung Park, Sungsoo Park, Taesung Kim. 184-186 [doi]
• A 0.91mW/element pitch-matched front-end ASIC with integrated subarray beamforming ADC for miniature 3D ultrasound probesChao Chen, Zhao Chen, Deep Bera, Emile Noothout, Zu-yao Chang, Mingliang Tan, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs. 186-188 [doi]
• Single-chip reduced-wire active catheter system with programmable transmit beamforming and receive time-division multiplexing for intracardiac echocardiographyGwangrok Jung, M. Wasequr Rashid, Thomas M. Carpenter, Coskun Tekes, David M. J. Cowell, Steven Freear, F. Levent Degertekin, Maysam Ghovanloo. 188-190 [doi]
• A 0.3ppm dual-resonance transformer-based drift-cancelling reference-free magnetic sensor for biosensing applicationsConstantine Sideris, Parham Porsandeh Khial, Bill Ling, Ali Hajimiri. 190-192 [doi]
• 2 1.89μVrms noise 12b biasing DACKiduk Kim, Seunghyun Park, Kye-Seok Yoon, Gyeong-Gu Kang, Hyun-Ki Han, Ji-Su Choi, Min-Woo Ko, Jeong-Hyun Cho, Sangjin Lim, Hyung-Min Lee, Hyunsik Kim, Kwyro Lee, Gyu-Hyeong Cho. 192-194 [doi]
• Session 11 overview: SRAM: Memory subcommitteeJonathan Chang, Chun Shiah, Leland Chang. 194-195 [doi]
• 2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applicationsZheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl. 196-198 [doi]
• A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applicationsTaejoong Song, Jonghoon Jung, Woojin Rim, Hoonki Kim, Yongho Kim, Changnam Park, Jeongho Do, Sunghyun Park, Sungwee Cho, Hyuntaek Jung, Bongjae Kwon, Hyun-Su Choi, Jaeseung Choi, Jong Shik Yoon. 198-200 [doi]
• A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applicationsMichael Clinton, Rajinder Singh, Marty Tsai, Shayan Zhang, Bryan Sheffield, Jonathan Chang. 200-201 [doi]
• Session 12 overview: DRAM: Memory subcommitteeSeung-Jun Bae, Wolfgang Spirkl, Leland Chang. 202-203 [doi]
• A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clockingYoung-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom, Young-Sik Kim, Min-Su Ahn, Yong Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung Bae Park, Jung-Bum Shin, Jong-Ho Lee, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Min-Woo Won, Gun-hee Cho, Hyun Soo Park, Hyung Kyu Kim, Jeong-Woo Lee, Seung Hyun Cho, Keon-Woo Park, Jae-Koo Park, Yong Jae Lee, Yong-Jun Kim, Young Hun Seo, Beob-Rae Cho, Chang-Ho Shin, Chanyong Lee, Youngseok Lee, Yoon-Gue Song, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byeong-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-jun Kwon, Jung Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang. 204-206 [doi]
• A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM processKi Chul Chun, Yong-Gyu Chu, Jin-Seok Heo, Tae Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sang-uhn Cha, Hyung Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim, Won Jun Choi, Dae-Sik Yim, Inkyu Moon, Young-Ju Kim 0001, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Young-Jae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seung Bum Ko, Jung Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang. 206-208 [doi]
• A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data controlJin-Hee Cho, Jihwan Kim, Wooyoung Lee, Dong Uk Lee, Tae-Kyun Kim, Heat Bit Park, Chunseok Jeong, Myeong-Jae Park, Seung Geun Baek, Seokwoo Choi, Byung Kuk Yoon, Young Jae Choi, Kyo Yun Lee, Daeyong Shim, Jonghoon Oh, Jinkook Kim, Seok Hee Lee. 208-210 [doi]
• A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applicationsKyu-Dong Hwang, Boram Kim, Sang-Yeon Byeon, Kyu-Young Kim, Dae-Han Kwon, Hyun Bae Lee, Geun-Il Lee, Sang-Sic Yoon, Jin-Youp Cha, Soo-young Jang, Seung Hun Lee, Yongsuk Joo, Gang-Sik Lee, Sung-Soo Xi, Soo-Bin Lim, Kyung-Ho Chu, Joohwan Cho, Junhyun Chun, Jonghoon Oh, Jinkook Kim, Seok Hee Lee. 210-212 [doi]
• A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with improved power distribution and repair strategySeokbo Shim, Sungho Kim, Jooyoung Bae, Keunsik Ko, Eunryeong Lee, Kwidong Kim, Kyeongtae Kim, Sangho Lee, Jinhoon Hyun, Insung Koh, Joonhong Park, Minjeong Kim, Sunhye Shin, Dongha Lee, Yunyoung Lee, Sangah Hyun, Wonjohn Choi, Dain Im, Dongheon Lee, Jieun Jang, Sangho Lee, Junhyun Chun, Jonghoon Oh, Jinkook Kim, Seok Hee Lee. 212-214 [doi]
• Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommitteeDejan Markovic, Masato Motomura, Byeong-Gyu Nam. 214-215 [doi]
• QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOSKodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura. 216-218 [doi]
• UNPU: A 50.6TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precisionJinmook Lee, Changhyeon Kim, Sanghoon Kang, Dongjoo Shin, Sangyeob Kim, Hoi-Jun Yoo. 218-220 [doi]
• A 9.02mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devicesSungpill Choi, Jinsu Lee, Kyuho Jason Lee, Hoi-Jun Yoo. 220-222 [doi]
• An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOSDaniel Bankman, Lita Yang, Bert Moons, Marian Verhelst, Boris Murmann. 222-224 [doi]
• A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOIWei Tang, Hemanth Prabhu, Liang Liu, Viktor Öwall, Zhengya Zhang. 224-226 [doi]
• A 232-to-1996KS/s robust compressive-sensing reconstruction engine for real-time physiological signals monitoringTing-Sheng Chen, Hung-chi Kuo, An-Yeu Wu. 226-228 [doi]
• Session 14 overview: High-resolution ADCs: Data converter subcommitteeMatt Straayer, Seung-Tak Ryu, Un-Ku Moon. 228-229 [doi]
• A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDRTao He 0001, Michael Ashburn, Stacy Ho, Yi Zhang 0023, Gabor C. Temes. 230-232 [doi]
• A 15.2-ENOB continuous-time ΔΣ ADC for a 200mVpp-linear-input-range neural recording front-endHariprasad Chandrakumar, Dejan Markovic. 232-234 [doi]
• nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structureShaolan Li, Bo Qiao, Miguel Gandara, Nan Sun. 234-236 [doi]
• A 1.1mW 200kS/s incremental ΔΣ ADC with a DR of 91.5dB using integrator slicing for dynamic power reductionPatrick Vogelmann, Michael Haas, Maurits Ortmanns. 236-238 [doi]
• A 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BWShoubhik Karmakar, Burak Gonen, Fabio Sebastiano, Robert H. M. van Veldhoven, Kofi A. A. Makinwa. 238-240 [doi]
• A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integratorSung-En Hsieh, Chih-Cheng Hsieh. 240-242 [doi]
• A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3ppm INLHongxing Li, Mark Maddox, Michael C. W. Coln, William Buckley, Derek Hummerston, Naveed Naeem. 242-244 [doi]
• Session 15 overview: RF PLLs: RF subcommitteeJiayoon Ru, Jaehyouk Choi, Piet Wambacq. 244-245 [doi]
• A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOSHanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, Akira Matsuzawa. 246-248 [doi]
• A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulationDmytro Cherniak, Luigi Grimaldi, Luca Bertulessi, Carlo Samori, Roberto Nonis, Salvatore Levantino. 248-250 [doi]
• 2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converterDaniel Weyer, Mehmet Batuhan Dayanik, Sunmin Jang, Michael P. Flynn. 250-252 [doi]
• A low-phase-noise digital bang-bang PLL with fast lock over a wide lock rangeLuca Bertulessi, Luigi Grimaldi, Dmytro Cherniak, Carlo Samori, Salvatore Levantino. 252-254 [doi]
• A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path couplingCheng-Ru Ho, Mike Shuo-Wei Chen. 254-256 [doi]
• 2 4.6-to-5.6GHz sub-sampling type-I frequency synthesizer with -254dB FOMAhmad Sharkia, Shahriar Mirabbasi, Sudip Shekhar. 256-258 [doi]
• A dividerless reference-sampling RF PLL with -253.5dB jitter FOM and <-67dBc Reference SpursJahnavi Sharma, Harish Krishnaswamy. 258-260 [doi]
• An 82-to-108GHz -181dB-FOMT ADPLL employing a DCO with split-transformer and dual-path switched-capacitor ladder and a clock-skew-sampling delta-sigma TDCZhiqiang Huang, Howard Cam Luong. 260-262 [doi]
• Session 16 overview: Advanced optical and wireline techniques: Wireline subcommitteeAzita Emami, Andrew K. Joy, Frank O'Mahony. 262-263 [doi]
• A 28Gb/s transceiver with chirp-managed EDC for DML systemsKyeongha Kwon, Jong-Hyeok Yoon, Hanho Choi, Younho Jeon, Jaehyeok Yang, Bongjin Kim, Soon-Won Kwon, Minsik Kim, Sejun Jeon, Hyosup Won, Hyeon-Min Bae. 264-266 [doi]
• A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOSIlter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Thomas Morf, Daniel M. Kuchta, Lukas Kull, Marcel A. Kossel, Danny Luu, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl. 266-268 [doi]
• A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOSAshwin Ramachandran, Tejasvi Anand. 268-270 [doi]
• A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOSSejun Jeon, Woohyun Kwon, Taehun Yoon, Jong-Hyeok Yoon, Kyeongha Kwon, Jaehyeok Yang, Hyeon-Min Bae. 270-272 [doi]
• A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfacesSooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jaehyun Ko, Jae-Yoon Sim, Hong June Park, Byungsub Kim. 272-274 [doi]
• A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFETMarc Erett, Declan Carey, James Hudner, Ronan Casey, Kevin Geary, Pedro Neto, Mayank Raj, Scott McLeod, Hongtao Zhang, Arianne Roldan, Hongyuan Zhao, Ping-Chuan Chiang, Haibing Zhao, Kee Hian Tan, Yohan Frans, Ken Chang. 274-276 [doi]
• A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulatorJohn M. Wilson 0002, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally. 276-278 [doi]
• A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communicationsYanghyo Kim, Boyu Hu, Yuan Du, Adrian Tang 0002, Huan-Neng Ron Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang. 278-280 [doi]
• Session 17 overview: Technologies for health and society: Technology directions subcommitteePatrick P. Mercier, Long Yan, Makoto Nagata. 280-281 [doi]
• 4-Camera VGA-resolution capsule endoscope with 80Mb/s body-channel communication transceiver and Sub-cm range capsule localizationJaeeun Jang, Jihee Lee, Kyoung-Rog Lee, Jiwon Lee, Minseo Kim, Yongsu Lee, Joonsung Bae, Hoi-Jun Yoo. 282-284 [doi]
• A 0.3V biofuel-cell-powered glucose/lactate biosensing system employing a 180nW 64dB SNR passive δς ADC and a 920MHz wireless transmitterAli Fazli Yeknami, Xiaoyang Wang 0003, Somayeh Imani, Ali Nikoofard, Itthipon Jeerapan, Joseph Wang, Patrick P. Mercier. 284-286 [doi]
• A 0.28mΩ-sensitivity 105dB-dynamic-range electrochemical impedance spectroscopy soc for electrochemical gas detectionGuangyang Qu, Hanqing Wang, Yimiao Zhao, John O'Donnell, Colin Lyden, Yincai Liu, Junbiao Ding, Dennis Dempsey, Leicheng Chen, Donal Bourke, Shurong Gu, Jun Gao, Lizhu Lu, Li Wang, Xuemin Li, Hongxing Li, Chao Chu, Ling Yang. 286-288 [doi]
• 50nW 5kHz-BW opamp-less ΔΣ impedance analyzer for brain neurochemistry monitoringMaged El Ansary, Nima Soltani, Hossein Kassiri, Ruben Machado, Suzie Dufour, Peter L. Carlen, Michael Thompson, Roman Genov. 288-290 [doi]
• A 200Mb/s inductively coupled wireless transcranial transceiver achieving 5e-11 BER and 1.5pJ/b transmit energy efficiencyWen Li, Yida Duan, Jan M. Rabaey. 290-292 [doi]
• A 330μm×90μm opto-electronically integrated wireless system-on-chip for recording of neural activitiesSunWoo Lee, Alejandro J. Cortese, Paige Trexel, Elizabeth R. Agger, Paul L. McEuen, Alyosha C. Molnar. 292-294 [doi]
• A 665μW silicon photomultiplier-based NIRS/EEG/EIT monitoring asic for wearable functional brain imagingJiawei Xu, Mario Konijnenburg, Budi Lukita, Shuang Song, Hyunsoo Ha, Roland Van Wegberg, Erfan Sheikhi, Massimo Mazzillo, Giorgio Fallica, Walter De Raedt, Chris Van Hoof, Nick Van Helleputte. 294-296 [doi]
• 2 Σ ADCs and Charge-Balanced Programmable Waveform NeurostimulatorsGerard O'Leary, Mohammad Reza Pazhouhandeh, Michael Chang, David Groppe, Taufik A. Valiante, Naveen Verma, Roman Genov. 296-298 [doi]
• Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommitteeDennis Sylvester, Koji Hirairi, Edith Beigné. 298-299 [doi]
• Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processorChristos Vezyrtzis, Thomas Strach, Pierce I-Jen Chuang, Preetham Lobo, Richard F. Rizzolo, Tobias Webel, Pawel Owczarczyk, Alper Buyuktosunoglu, Ramon Bertran, David T. Hui, Susan M. Eickhoff, Michael S. Floyd, Gerard Salem, Sean M. Carey, Stelios G. Tsapepas, Phillip J. Restle. 300-302 [doi]
• A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processorXun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li, Naveen John, Visvesh S. Sathe. 302-304 [doi]
• 2 automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD rangeAnthony Quelen, Gaël Pillonnet, Philippe Flatresse, Edith Beigné. 304-306 [doi]
• A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOSXiaofei Ma, Yan Lu, Rui P. Martins, Qiang Li. 306-308 [doi]
• A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioningSomnath Kundu, Muqing Liu, Richard Wong, Shi-Jie Wen, Chris H. Kim. 308-310 [doi]
• A 500mA analog-assisted digital-LDO-based on-chip distributed power delivery grid with cooperative regulation and IR-drop reduction in 65nm CMOSYasu Lu, Fan Yang 0006, Feng Chen, Philip K. T. Mok. 310-312 [doi]
• A sub-1.55mV-accuracy 36.9ps-FOM digital-low-dropout regulator employing switched-capacitor resistanceLoai G. Salem, Patrick P. Mercier. 312-314 [doi]
• A high-efficiency and fast-transient digital-low-dropout regulator with the burst mode corresponding to the power-saving modes of DC-DC switching convertersJian-He Lin, Yu-Sheng Ma, Chia-Ming Huang, Li-Chi Lin, Chiao-Hung Cheng, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 314-316 [doi]
• Session 19 overview: Sensors and interfaces: Analog subcommitteeMan Kay Law, Taeik Kim, Kofi Makinwa. 316-317 [doi]
• An 8b subthreshold hybrid thermal sensor with ±1.07°C inaccuracy and single-element remote-sensing technique in 22nm FinFETCho-Ying Lu, Surej Ravikumar, Amruta D. Sali, Matthias Eberlein, Hyung-Jin Lee. 318-320 [doi]
• 2Sining Pan, Kofi A. A. Makinwa. 320-322 [doi]
• 2 resistor-based temperature sensor with an inaccuracy of ±0.35°C (3σ) in 65nm CMOSWoojun Choi, Yong-Tae Lee, Seonhong Kim, Sanghoon Lee, Jieun Jang, Junhyun Chun, Kofi A. A. Makinwa, Youngcheol Chae. 322-324 [doi]
• A ±4A high-side current sensor with 25V input CM range and 0.9% gain error from -40°C to 85°C using an analog temperature compensation techniqueLong Xu, Johan H. Huijsing, Kofi A. A. Makinwa. 324-326 [doi]
• A current-measurement front-end with 160dB dynamic range and 7ppm INLChung-Lun Hsu, Drew A. Hall. 326-328 [doi]
• 3 pressure-sensing systemSechang Oh, Yao Shi, Gyouho Kim, Yejoong Kim, Taewook Kang, Seokhyeon Jeong, Dennis Sylvester, David Blaauw. 328-330 [doi]
• A 21.8b sub-100μHz 1/f corner 2.4μV-offset programmable-gain read-out IC for bridge measurement systemsJaehoon Jun, Cyuyeol Rhee, MinSung Kim, Junho Kang, Suhwan Kim. 330-332 [doi]
• A phase-domain readout circuit for a CMOS-compatible thermal-conductivity-based carbon dioxide sensorZeyu Cai, Robert H. M. van Veldhoven, Hilco Suy, Ger de Graaf, Kofi A. A. Makinwa, Michiel Pertijs. 332-334 [doi]
• Session 20 overview: Flash-memory solutions: Memory subcommitteeKi Tae Park, Yan Li, Leland Chang. 334-335 [doi]
• A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technologyHiroshi Maejima, Kazushige Kanda, Susumu Fujimura, Teruo Takagiwa, Susumu Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Naohito Morozumi, Ryo Fukuda, Yuui Shimizu, Toshifumi Hashimoto, Xu Li, Yuki Shimizu, Kenichi Abe, Tadashi Yasufuku, Takatoshi Minamoto, Hiroshi Yoshihara, Takahiro Yamashita, Kazuhiko Satou, Takahiro Sugimoto, Fumihiro Kono, Mitsuhiro Abe, Tomoharu Hashiguchi, Masatsugu Kojima, Yasuhiro Suematsu, Takahiro Shimizu, Akihiro Imamoto, Naoki Kobayashi 0004, Makoto Miakashi, Kouichirou Yamaguchi, Sanad Bushnaq, Hicham Haibi, Masatsugu Ogawa, Yusuke Ochi, Kenro Kubota, Taichi Wakui, Dong He, Weihan Wang, Hiroe Minagawa, Tomoko Nishiuchi, Hao Nguyen, Kwang Ho Kim, Ken Cheah, Yee Koh, Feng Lu, Venky Ramachandra, Srinivas Rajendra, Steve Choi, Keyur Payak, Namas Raghunathan, Spiros Georgakis, Hiroshi Sugawara, Seungpil Lee, Takuya Futatsuyama, Koji Hosono, Noboru Shibata, Toshiki Hisada, Tetsuya Kaneko, Hiroshi Nakamura. 336-338 [doi]
• A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read timeWooseong Cheong, Chanho Yoon, SeongHoon Woo, Kyuwook Han, Daehyun Kim, Chulseung Lee, Youra Choi, Shine Kim, Dongku Kang, Geunyeong Yu, Jaehong Kim, Jaechun Park, Ki-Whan Song, Ki Tae Park, Sangyeun Cho, Hwaseok Oh, Daniel D. G. Lee, Jin Hyeok Choi, Jaeheon Jeong. 338-340 [doi]
• A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughputSeungjae Lee, Chulbum Kim, Minsu Kim, Sung-Min Joe, Joonsuc Jang, SeungBum Kim, Kangbin Lee, Jisu Kim, Jiyoon Park, Hanjun Lee, Min-Seok Kim, Seonyong Lee, SeonGeon Lee, Jinbae Bang, Dongjin Shin, Hwajun Jang, Deokwoo Lee, Nahyun Kim, Jonghoo Jo, Jonghoon Park, Sohyun Park, Youngsik Rho, Yongha Park, Ho Joon Kim, Cheon An Lee, Chungho Yu, Young-Sun Min, Moosung Kim, Kyungmin Kim, SeungHyun Moon, Hyun-Jin Kim, Youngdon Choi, YoungHwan Ryu, Jinwon Choi, Minyeong Lee, Jungkwan Kim, Gyo Soo Choo, Jeong-Don Lim, Dae-Seok Byeon, Ki-Whan Song, Ki Tae Park, Kyehyun Kyung. 340-342 [doi]
• Session 21 overview: Extending silicon and its applications: Technology directions subcommitteeJan Genoe, Frederic Gianesello, Makoto Nagata. 342-343 [doi]
• Mixed-signal programmable non-linear interface for resource-efficient multi-sensor analyticsKomail M. H. Badami, Juan Carlos Pena Ramos, Steven Lauwereins, Marian Verhelst. 344-346 [doi]
• A 1μW voice activity detector using analog feature extraction and digital deep neural networkMinhao Yang, Chung-Heng Yeh, Yiyin Zhou, Joao Pedro Cerqueira, Aurel A. Lazar, Mingoo Seok. 346-348 [doi]
• 32GHz resonant-fin transistors in 14nm FinFET technologyBichoy Bahr, Yanbo He, Zoran Krivokapic, Srinivasa Banna, Dana Weinstein. 348-350 [doi]
• 2 Die-to-Die Optical NetworksYvain Thonnart, Mounir Zid, Jose-Luis Gonzalez Jimenez, Guillaume Waltener, Robert Polster, Olivier Dubray, Florent Lepin, Stephane Bernabe, Sylvie Menezo, Gabriel Pares, Olivier Castany, Laura Boutafa, Philippe Grosse, Benoît Charbonnier, Charles Baudot. 350-352 [doi]
• 2/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attackKohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura. 352-354 [doi]
• An 8-channel 13GHz ESR-on-a-Chip injection-locked vco-array achieving 200μM-concentration sensitivityAnh Chu, Benedikt Schlecker, Klaus Lips, Maurits Ortmanns, Jens Anders. 354-356 [doi]
• Session 22 overview: Gigahertz data converters: Data converter subcommitteeKostas Doris, Jan Westra, Un-Ku Moon. 356-357 [doi]
• A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFETLukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl. 358-360 [doi]
• A 16b 6GS/S nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOSChi-Hung Lin, Jackie Koon Lun Wong, Tae Youn Kim, Guangxi Ray Xie, Donald Major, Greg Unruh, Sunny Raj Dommaraju, Hans Eberhart, Ardie Venes. 360-362 [doi]
• A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbandsShiyu Su, Mike Shuo-Wei Chen. 362-364 [doi]
• Session 23 overview: LO generation: RF subcommitteeHyunchol Shin, Andrea Bevilacqua, Piet Wambacq. 364-365 [doi]
• A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliersHeein Yoon, Juyeop Kim, Suneui Park, Younghyun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi. 366-368 [doi]
• A >40dB IRR, 44% fractional-bandwidth ultra-wideband mm-wave quadrature LO generator for 5G networks in 55nm CMOSFarshad Piri, Matteo Bassi, Niccolo Lacaita, Andrea Mazzanti, Francesco Svelto. 368-370 [doi]
• A 22.8-to-43.2GHz tuning-less injection-locked frequency tripler using injection-current boosting with 76.4% locking range for multiband 5G applicationsJingzhi Zhang, Huihua Liu, Chenxi Zhao, Kai Kang. 370-372 [doi]
• A 301.7-to-331.8GHz source with entirely on-chip feedback loop for frequency stabilization in 0.μm BiCMOSChen Jiang, Mohammed Aseeri, Andreia Cathelin, Ehsan Afshari. 372-374 [doi]
• 3 phase-noise suppression achieving 196.2dBc/Hz FOMChee-Cheow Lim, Jun Yin, Pui-In Mak, Harikrishnan Ramiah, Rui P. Martins. 374-376 [doi]
• A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillationsFabio Padovan, Fabio Quadrelli, Matteo Bassi, Marc Tiebout, Andrea Bevilacqua. 376-378 [doi]
• A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCsDidem Turker, Ade Bekele, Parag Upadhyaya, Bob Verbruggen, Ying Cao, Shaojun Ma, Christophe Erdmann, Brendan Farley, Yohan Frans, Ken Chang. 378-380 [doi]
• Session 24 overview: GaN drivers and converters: Power management subcommitteeYogesh K. Ramadass, Gerard Villar Pique, Axel Thomsen. 380-381 [doi]
• A 2MHz 150-to-400V input isolated DC-DC bus converter with monolithic slope-sensing ZVS detection achieving 13ns turn-on delay and 1.6W power savingLin Cong, Hoi Lee. 382-384 [doi]
• A fully integrated three-level 11.6nC gate driver supporting GaN gate injection transistorsAchim Seidel, Bernhard Wicht. 384-386 [doi]
• A 3-to-40V VIN 10-to-50MHz 12W isolated GaN driver with self-excited tdead minimizer achieving 0.2ns/0.3ns tdead, 7.9% minimum duty ratio and 50V/ns CMTIXugang Ke, Dongsheng Brian Ma. 386-388 [doi]
• Session 25 overview: Clock generation for high-speed links: Wireline subcommitteeRoberto Nonis, Pavan Hanumolu, Frank O'Mahony. 388-389 [doi]
• A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFETStanley Chen, Lei Zhou, Ian Zhuang, Jay Im, Didem Turkur Melek, Jinyung Namkoong, Mayank Raj, Jaewook Shin, Yohan Frans, Ken Chang. 390-392 [doi]
• A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOSKarim M. Megawer, Ahmed Elkholy, Daniel Coombs, Mostafa Gamal Ahmed, Ahmed Elmallah, Pavan Kumar Hanumolu. 392-394 [doi]
• A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOSCheng-Ru Ho, Mike Shuo-Wei Chen. 394-396 [doi]
• A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDCTaeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi. 396-398 [doi]
• Session 26 overview: RF techniques for communication and sensing: RF subcommitteeGiuseppe Gramegna, Hua Wang, Piet Wambacq. 398-399 [doi]
• A 0.55-to-0.9GHz 2.7dB NF full-duplex hybrid-coupler circulator with 56MHz 40dB TX SI suppressionSanket Jain, Abhishek Agrawal, Manoj Johnson, Arun Natarajan. 400-402 [doi]
• A 62-to-68GHz linear 6Gb/s 64QAM CMOS doherty radiator with 27.5%/20.1% PAE at peak/6dB-back-off output power leveraging high-efficiency multi-feed antenna-based active load modulationHuy Thong Nguyen, Taiyun Chi, Sensen Li, Hua Wang. 402-404 [doi]
• A 69-to-79GHz CMOS multiport PA/radiator with +35.7dBm CW EIRP and integrated PLLBehrooz Abiri, Ali Hajimiri. 404-406 [doi]
• A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arraysSheikh Nijam Ali, Pawan Agarwal, Joe Baylon, Srinivasan Gopal, Luke Renaud, Deukhyoun Heo. 406-408 [doi]
• A compact dual-band digital doherty power amplifier using parallel-combining transformer for cellular NB-IoT applicationsYun Yin, Liang Xiong, Yiting Zhu, Bowen Chen, Hao Min, Hongtao Xu. 408-410 [doi]
• A continuous-mode harmonically tuned 19-to-29.5GHz ultra-linear PA supporting 18Gb/s at 18.4% modulation PAE and 43.5% peak PAETso-Wei Li, Ming-Yu Huang, Hua Wang. 410-412 [doi]
• A coupled-RTWO-based subharmonic receiver front-end for 5G E-Band backhaul links in 28nm bulk CMOSMarco Vigilante, Patrick Reynaert. 412-414 [doi]
• A 12mW 70-to-100GHz mixer-first receiver front-end for mm-wave massive-MIMO arrays in 28nm CMOSLorenzo Lotti, Greg LaCaille, Ali M. Niknejad. 414-416 [doi]
• th-order CMOS reconfigurable RF BPF with adjustable transmission zeros for SAW-less SDR receiversPingyue Song, Hossein Hashemi. 416-418 [doi]
• A 128-pixel 0.56THz sensing array for real-time near-field imaging in 0.13μm SiGe BiCMOSPhilipp Hillger, Ritesh Jain, Janusz Grzyb, Laven Mavarani, Bernd Heinemann, Gaetan Mac Grogan, Patrick Mounaix, Thomas Zimmer, Ullrich R. Pfeiffer. 418-420 [doi]
• Session 27 overview: Power-converter techniques: Power management subcommitteeMakoto Takamiya, Yen Hsun Hsu, Axel Thomsen. 420-421 [doi]
• 2Yang Jiang, Man Kay Law, Pui-In Mak, Rui P. Martins. 422-424 [doi]
• A 10MHz time-domain-controlled current-mode buck converter with 8.5% to 93% switching duty cycleJin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, Changsik Yoo. 424-426 [doi]
• An 86% efficiency SIMO DC-DC converter with one boost, one buck, and a floating output voltage for car-radioArunkumar Salimath, Edoardo Bonizzoni, Edoardo Botti, Giovanni Gonano, Paolo Cacciagrano, Davide Luigi Brambilla, Tommaso Barbieri, Franco Maloberti. 426-428 [doi]
• A 97% high-efficiency 6μs fast-recovery-time buck-based step-up/down converter with embedded 1/2 and 3/2 charge-pumps for li-lon battery managementMin-Woo Ko, Kiduk Kim, Young-Jin Woo, Se-un Shin, Hyun-Ki Han, Yeunhee Huh, Gyeong-Gu Kang, Jeong-Hyun Cho, Sang-Jin Lim, Se-Hong Park, Hyung-Min Lee, Gyu-Hyeong Cho. 428-430 [doi]
• A 95.2% efficiency dual-path DC-DC step-up converter with continuous output current delivery and low voltage rippleSe-un Shin, Yeunhee Huh, Yong-Min Ju, Sung-Won Choi, Changsik Shin, Young-Jin Woo, Minseong Choi, Se-Hong Park, Young-Hoon Sohn, Min-Woo Ko, Youngsin Jo, Hyun-Ki Han, Hyung-Min Lee, Sung-Wan Hong, Wanyuan Qu, Gyu-Hyeong Cho. 430-432 [doi]
• An 87.1% efficiency RF-PA envelope-tracking modulator for 80MHz LTE-Advanced transmitter and 31dBm PA output power for HPUE in 0.153μm CMOSChen-Yen Ho, Shih-Mei Lin, Che-Hao Meng, Hao-Ping Hong, Sheng-Hong Yan, Ting-Hsun Kuo, Chia-Sheng Peng, Chieh-Hsun Hsiao, Hsin-Hung Chen, Da-Wei Sung, Chien-Wei Kuan. 432-434 [doi]
• A 2TX supply modulator for envelope-tracking power amplifier supporting intra- and inter-band uplink carrier aggregation and power class-2 high-power user equipmentTakahiro Nomiyama, Yong-Sik Youn, Young-Hwan Choo, Dong-Su Kim, Jae-Yeol Han, Jun-Hee Jung, Jongbeom Baek, Sung-Jun Lee, Euiyoung Park, Jeong-Hyun Choi, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang. 434-436 [doi]
• 94% power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phoneWei-Chung Chen, Tzu-Chi Huang, Chao-Chang Chiu, Chih-Wei Chang, Kuo-Chun Hsu. 436-438 [doi]
• 2 current density and 0.4V outputMoataz Abdelfattah, Muhammad Swilam, Brian Dupaix, Shane Smith, Ayman Fayed, Waleed Khalil. 438-440 [doi]
• Session 28 overview: Wireless connectivity: Wireless subcommitteeHoward Luong, Kyoo Hyun Lim, Stefano Pellerano. 440-441 [doi]
• An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzerShusuke Kawai, Hiromitsu Aoyama, Rui Ito, Yutaka Shimizu, Mitsuyuki Ashida, Asuka Maki, Tomohiko Takeuchi, Hiroyuki Kobayashi, Go Urakawa, Hiroaki Hoshino, Shigehito Saigusa, Kazushi Koyama, Makoto Morita, Ryuichi Nihei, Daisuke Goto, Motoki Nagata, Kengo Nakata, Katsuyuki Ikeuchi, Kentaro Yoshioka, Ryoichi Tachibana, Makoto Arai, Chen Kong Teh, Atsushi Suzuki, Hiroshi Yoshida, Yosuke Hagiwara, Takayuki Kato, Ichiro Seto, Tomoya Horiguchi, Koichiro Ban, Kyosuke Takahashi, Hirotsugu Kajihara, Toshiyuki Yamagishi, Yuki Fujimura, Kazuhisa Horiuchi, Katsuya Nonin, Kengo Kurose, Hideki Yamada, Kentaro Taniguchi, Masahiro Sekiya, Takeshi Tomizawa, Daisuke Taki, Masaaki Ikuta, Tomoya Suzuki, Yuki Ando, Daisuke Yashima, Takahisa Kaihotsu, Hiroki Mori, Kensuke Nakanishi, Takeshi Kumagaya, Yasuo Unekawa, Tsuguhide Aoki, Kohei Onizuka, Toshiya Mitomo. 442-444 [doi]
• An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOSHanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Kenichi Okada, Akira Matsuzawa. 444-446 [doi]
• 2 bluetooth 5/BLE digital-intensive transceiver with a 2.3mW phase-tracking RX utilizing a hybrid loop filter for interference resilience in 40nm CMOSMing Ding, Xiaoyan Wang, Peng Zhang, Yuming He, Stefano Traferro, Kenichi Shibata, Minyoung Song, Hannu Korpela, Keisuke Ueda, Yao-Hong Liu, Christian Bachmann, Kathleen Philips. 446-448 [doi]
• A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz referenceMin-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Robert Bogdan Staszewski. 448-450 [doi]
• A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOSJun Yin, Shiheng Yang, Haidong Yi, Wei-Han Yu, Pui-In Mak, Rui P. Martins. 450-452 [doi]
• A -76dBm 7.4nW wakeup radio with automatic offset compensationJesse Moody, Pouyan Bassirian, Abhishek Roy, Ningxi Liu, Stephen Pancrazio, N. Scott Barker, Benton H. Calhoun, Steven M. Bowers. 452-454 [doi]
• 2 8nW -59.7dBm-sensitivity ultrasonic wake-up receiver for power-, area-, and interference-constrained applicationsAngad Singh Rekhi, Amin Arbabian. 454-456 [doi]
• A 5.8GHz power-harvesting 116μmx116μm "dielet" near-field radio with on-chip coil antennaBo Zhao 0003, Nai-Chung Kuo, Benyuanyi Liu, Yi-An Li, Lorenzo Lotti, Ali M. Niknejad. 456-458 [doi]
• Session 29 overview: Advanced biomedical systems: IMMD subcommitteePedram Mohseni, Nick Van Helleputte, Makoto Ikeda. 458-459 [doi]
• Creating neural "co-processors" to explore treatments for neurological disordersScott Stanslaski, Jeffrey Herron, Elizabeth Fehrmann, Rob Corey, Heather Orser, Enrico Opri, Václav Kremen, Ben Brinkmann, Aysegul Gunduz, Kelly Foote, Greg Worrell, Tim Denison. 460-462 [doi]
• A fully immersible deep-brain neural probe with modular architecture and a delta-sigma ADC integrated under each electrode for parallel readout of 144 recording sitesDaniel DeDorigo, Christian Moranz, Hagen Graf, Maximilian Marx 0002, Boyu Shui, Matthias Kuhl, Yiannos Manoli. 462-464 [doi]
• A 16384-electrode 1024-channel multimodal CMOS MEA for high-throughput intracellular action potential measurements and impedance spectroscopy in drug-screening applicationsCarolina Mora Lopez, Ho Sung Chun, Laurent Berti, Shiwei Wang, Jan Putzeys, Carl Van Den Bulcke, Jan-Willem Weijers, Andrea Firrincieli, Veerle Reumers, Dries Braeken, Nick Van Helleputte. 464-466 [doi]
• A 13μm CMOS SoC for simultaneous multichannel optogenetics and electrophysiological brain recordingGabriel Gagnon-Turcotte, Christian Ethier, Yves De Koninck, Benoit Gosselin. 466-468 [doi]
• A mm-sized free-floating wirelessly powered implantable optical stimulating system-on-a-chipYaoyao Jia, S. Abdollah Mirbozorgi, Byunghun Lee, Wasif Khan, Fatma Madi, Arthur J. Weber, Wen Li, Maysam Ghovanloo. 468-470 [doi]
• A 92dB dynamic range sub-μVrms-noise 0.8μW/ch neural-recording ADC array with predictive digital autorangingChul Kim, Siddharth Joshi, Hristos Courellis, Jun Wang 0040, Cory Miller, Gert Cauwenberghs. 470-472 [doi]
• A 110dB-CMRR 100dB-PSRR multi-channel neural-recording amplifier system using differentially regulated rejection ratio enhancement in 0.18μm CMOSSehwan Lee, Arup K. George, Taeju Lee, Jun-Uk Chu, Sungmin Han, Ji-Hoon Kim, Minkyu Je, Junghyup Lee. 472-474 [doi]
• A 43.4μW photoplethysmogram-based heart-rate sensor using heart-beat-locked loopDo-Hun Jang, SeongHwan Cho. 474-476 [doi]
• Session 30 overview: Emerging memories: Memory and technology directions subcommitteesShinichiro Shiratake, Edoardo Charbon, Leland Chang, Makoto Nagata. 476-477 [doi]
• An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performanceChung-Cheng Chou, Zheng-Jun Lin, Pei-Ling Tseng, Chih-Feng Li, Chih-Yang Chang, Wei-Chi Chen, Yu-Der Chih, Tsung-Yung Jonathan Chang. 478-480 [doi]
• A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-terminationQing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang 0002, Yi-Chun Shih, Yu-Der Chih, Jonathan Chang, David Blaauw, Dennis Sylvester. 480-482 [doi]
• A 28nm 32Kb embedded 2T2MTJ STT-MRAM macro with 1.3ns read-access time for fast and reliable read applicationsTzu-Hsien Yang, Kai-Xiang Li, Yen-Ning Chiang, Wei-Yu Lin, Huan-Ting Lin, Meng-Fan Chang. 482-484 [doi]
• 14-cycle endurance memory module composed of 60nm crystalline oxide semiconductor transistorsShuhei Maeda, Satoru Ohshita, Kazuma Furutani, Yuto Yakubo, Takahiko Ishizu, Tomoaki Atsumi, Yoshinori Ando, Daisuke Matsubayashi, Kiyoshi Kato, Takashi Okuda, Masahiro Fujita, Shunpei Yamazaki. 484-486 [doi]
• Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommitteesNaveen Verma, Fatih Hamzaoglu, Makoto Nagata, Leland Chang. 486-487 [doi]
• Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applicationsAvishek Biswas, Anantha P. Chandrakasan. 488-490 [doi]
• A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip trainingSujan Kumar Gonugondla, Mingu Kang, Naresh Shanbhag. 490-492 [doi]
• Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case studyTony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra. 492-494 [doi]
• A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processorsWei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li, Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang. 494-496 [doi]
• A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processorsWin-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang. 496-498 [doi]
• Tutorials: Low-Jitter PLLs for wireless transceiversXiang Gao. 499-501 [doi]
• F1: Intelligent energy-efficient systems at the edge of IoTVivek De, Dennis Sylvester, James Myers, Jun Deguchi, Shinichiro Shiratake, Ingrid Verbauwhede. 502-504 [doi]
• F2: FinFETs & FDSOI - A mixed signal circuit designer's perspectiveVenkatesh Srinivasan, Stephane Le Tuai, Tai-Cheng Lee. 505-507 [doi]
• F3: Circuits and architectures for wireless sensing, radar and imagingBrian P. Ginsburg. 508-510 [doi]
• F4: Circuit and system techniques for mm-wave multi-antenna systemsPierre Busson, Howard Luong, Chih-Ming Hung, Harish Krishnaswamy, Theodore Georgantas, Patrick P. Mercier. 511-513 [doi]
• F5: Advanced optical communication: From devices, circuits, and architectures to algorithmsBo Zhang, Frederic Gianesello, Simone Erba, Mounir Meghelli, Azita Emami, Takayuki Shibasaki. 514-516 [doi]
• F6: Advances in energy efficient analog designAxel Thomsen, Bernhard Wicht, Pieter Harpe, Man Kay Law, Young Cheol Chae. 517-519 [doi]
• EE2: Workshop on circuits for social goodVivienne Sze, Alison Burdett, Sonia Leon, Rikky Muller, Farhana Sheikh, Yildiz Sinangil, Trudy Stetzler, Ingrid Verbauwhede, Alice Wang, Rabia Tugce Yazicigil. 523-525 [doi]
• EE3: Industry showcaseAlison Burdett, Eugenio Cantatore, Kush Gulati, Yan Li. 525-527 [doi]
• EE4: Figures-of-merit on trialKostas Doris, Stefano Stanzione, Paul Ferguson. 527-529 [doi]
• EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!)Phillip Restle, Kostas Doris, Vivek De, Paul Ferguson. 529-531 [doi]
• EE6: Can artificial intelligence replace my job? The dawn of a new IC industry with AIJaeha Kim, Ki Tae Park. 531-533 [doi]
• SC: Hardware approaches to machine learning and inferenceDaniel Friedman. 533-534 [doi]