Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li, Naveen John, Visvesh S. Sathe. A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 302-304, IEEE, 2018. [doi]
Abstract is missing.