A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS

Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao-xiang, Kai Sheng, Ai He. A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 114-116, IEEE, 2018. [doi]

Abstract

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