Shiheng Yang, Jun Yin, Pui-In Mak, Rui P. Martins. 2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 118-120, IEEE, 2018. [doi]
Abstract is missing.