Shiheng Yang, Jun Yin, Pui-In Mak, Rui P. Martins. 2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 118-120, IEEE, 2018. [doi]
@inproceedings{YangYMM18,
title = {2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM},
author = {Shiheng Yang and Jun Yin and Pui-In Mak and Rui P. Martins},
year = {2018},
doi = {10.1109/ISSCC.2018.8310212},
url = {https://doi.org/10.1109/ISSCC.2018.8310212},
researchr = {https://researchr.org/publication/YangYMM18},
cites = {0},
citedby = {0},
pages = {118-120},
booktitle = {2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018},
publisher = {IEEE},
isbn = {978-1-5090-4940-0},
}