A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Ki Chul Chun, Yong-Gyu Chu, Jin-Seok Heo, Tae Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sang-uhn Cha, Hyung Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim, Won Jun Choi, Dae-Sik Yim, Inkyu Moon, Young-Ju Kim 0001, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Young-Jae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seung Bum Ko, Jung Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang. A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 206-208, IEEE, 2018. [doi]