A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

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Ki Chul Chun, Yong-Gyu Chu, Jin-Seok Heo, Tae Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sang-uhn Cha, Hyung Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim, Won Jun Choi, Dae-Sik Yim, Inkyu Moon, Young-Ju Kim 0001, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Young-Jae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seung Bum Ko, Jung Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang. A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 206-208, IEEE, 2018. [doi]

@inproceedings{ChunCHKKYKLKYSC18,
  title = {A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process},
  author = {Ki Chul Chun and Yong-Gyu Chu and Jin-Seok Heo and Tae Sung Kim and Soohwan Kim and Hui-Kap Yang and Mi-Jo Kim and Chang-Kyo Lee and Ju-Hwan Kim and Hyunchul Yoon and Chang-Ho Shin and Sang-uhn Cha and Hyung Jin Kim and Young-Sik Kim and Kyungryun Kim and Young-Ju Kim and Won Jun Choi and Dae-Sik Yim and Inkyu Moon and Young-Ju Kim 0001 and Junha Lee and Young Choi and Yongmin Kwon and Sung-Won Choi and Jung-Wook Kim and Yoon-Suk Park and Woongdae Kang and Jinil Chung and Seunghyun Kim and Yesin Ryu and Seong Jin Cho and Hoon Shin and Hangyun Jung and Sanghyuk Kwon and Kyuchang Kang and Jongmyung Lee and Yujung Song and Young-Jae Kim and Eun-Ah Kim and Kyung-Soo Ha and Kyoung-Ho Kim and Seok-Hun Hyun and Seung Bum Ko and Jung Hwan Choi and Young-Soo Sohn and Kwang-Il Park and Seong-Jin Jang},
  year = {2018},
  doi = {10.1109/ISSCC.2018.8310256},
  url = {https://doi.org/10.1109/ISSCC.2018.8310256},
  researchr = {https://researchr.org/publication/ChunCHKKYKLKYSC18},
  cites = {0},
  citedby = {0},
  pages = {206-208},
  booktitle = {2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018},
  publisher = {IEEE},
  isbn = {978-1-5090-4940-0},
}

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A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process