Sudhir S. Kudva - researchr alias

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Viewing Publication 1 - 17 from 17

2024

16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and MaskingSudhir S. Kudva, Mahmut Ersin Sinangil, Stephen G. Tell, Nikola Nedovic, Sanquan Song, Brian Zimmer, C. Thomas Gray. isscc 2024: 302-304 [doi]

2022

An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET ProcessSanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray. vlsit 2022: 146-147 [doi]

2020

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package LinksXi Chen 0033, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson 0002, C. Thomas Gray. isscc 2020: 126-128 [doi]

2019

2018

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulatorJohn M. Wilson 0002, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally. isscc 2018: 276-278 [doi]

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control moduleSudhir S. Kudva, Sanquan Song, John W. Poulton, John M. Wilson 0002, Wenxu Zhao, C. Thomas Gray. cicc 2018: 1-4 [doi]

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnectsWalker J. Turner, John W. Poulton, John M. Wilson 0002, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray. cicc 2018: 1-8 [doi]

2016

Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive ClocksDivya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun. async 2016: 75-82 [doi]

2014

High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVSSudhir S. Kudva, Saurabh Chaubey, Ramesh Harjani. cicc 2014: 1-4 [doi]

2013

Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation TechniqueSudhir S. Kudva, Ramesh Harjani. jssc, 48(8):1910-1920, 2013. [doi]

2012

Fully integrated capacitive converter with all digital ripple mitigationSudhir S. Kudva, Ramesh Harjani. cicc 2012: 1-4 [doi]

2011

Fully-Integrated On-Chip DC-DC Converter With a 450X Output RangeSudhir S. Kudva, Ramesh Harjani. jssc, 46(8):1940-1951, 2011. [doi]

2010

Fully integrated on-chip DC-DC converter with a 450x output rangeSudhir S. Kudva, Ramesh Harjani. cicc 2010: 1-4 [doi]

2008

Quadrature generation techniques for frequency multiplication based oscillatorsJagdish Nayayan Pandey, Bharadwaj Amrutur, Sudhir S. Kudva. iscas 2008: 440-443 [doi]

2007

A Low Power Frequency Multiplication Technique for ZigBee TranscieverJagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj Amrutur. vlsid 2007: 150-155 [doi]

2004

Quality and complexity comparison of H.264 intra mode with JPEG2000 and JPEGAravind Al, Bindu P. Rao, Sudhir S. Kudva, Sreenu Babu, David S. Sumam, Ajit V. Rao. icip 2004: 525-528 [doi]

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