Abstract is missing.
- Asynchronously Controlled Frequency Locked LoopSuwen Yang, Frankie Y. Liu, Vincent C. Lee. 3-10 [doi]
- Analysis and Design of Delay Lines for Dynamic Voltage Scaling ApplicationsRamy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel. 11-18 [doi]
- Ring Oscillator Clocks and MarginsJordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar. 19-26 [doi]
- Gradual SynchronizationSandra J. Jackson, Rajit Manohar. 29-36 [doi]
- Fault Classification of the Error Detection Logic in the Blade Resilient TemplateFelipe A. Kuentzer, Alexandre M. Amory. 37-42 [doi]
- Adding Conditionality to Resilient Bundled-Data DesignsDylan Hand, Austin Katrin, William Koven. 43-44 [doi]
- Finding Glitches Using Formal MethodsYan Peng, Ian W. Jones, Mark R. Greenstreet. 45-46 [doi]
- Efficient Metastability-Containing Gray Code 2-SortChristoph Lenzen, Moti Medina. 49-56 [doi]
- The Metastable Behavior of a Schmitt-TriggerAndreas Steininger, Jürgen Maier, Robert Najvirt. 57-64 [doi]
- GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated CircuitsMilan Babic, Steffen Zeidler, Milos Krstic. 67-74 [doi]
- Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive ClocksDivya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun. 75-82 [doi]
- Automatic Clock: A Promising Approach toward GALSificationMahdi Jelodari Mamaghani, Milos Krstic, Jim D. Garside. 83-84 [doi]
- Low Power QDI Asynchronous FFTBenjamin Z. Tang, Frank Lane. 87-88 [doi]
- Qualifying Relative Timing Constraints for Asynchronous CircuitsJotham Vaddaboina Manoranjan, Kenneth S. Stevens. 91-98 [doi]
- Optimising Bundled-Data Balsa CircuitsNorman Kluge, Ralf Wollowski. 99-106 [doi]
- Specification Mining for Asynchronous ControllersJavier de San Pedro, Thomas Bourgeat, Jordi Cortadella. 107-114 [doi]