Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel. Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. In 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016, Porto Alegre, Brazil, May 8-11, 2016. pages 11-18, IEEE Computer Society, 2016. [doi]
Abstract is missing.