Abstract is missing.
- Reliability modeling of HK MG technologiesTanya Nigam, Andreas Kerber. 1-8 [doi]
- A 1.6-2.2GHz 23dBm low loss integrated CMOS duplexerMohamed Elkholy, Mohyee Mikhemar, Hooman Darabi, Kamran Entesari. 1-4 [doi]
- Wireline transceiversAzita Emami, Kimo Tam. 1 [doi]
- A mm-sized implantable device with ultrasonic energy transfer and RF data uplink for high-power applicationsJayant Charthad, Marcus J. Weber, Ting-Chia Chang, Mahmoud Saadat, Amin Arbabian. 1-4 [doi]
- Inverting buck-boost DC-DC converter for mobile AMOLED display with real-time self-tuned minimum power-loss tracking schemeSung-Wan Hong, Gyu-Hyeong Cho. 1-4 [doi]
- A 0.8V 140nW low-noise energy harvesting CMOS APS imager with fully digital readoutIsmail Cevik, Suat U. Ay. 1-4 [doi]
- A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signalsBongjin Kim, Somnath Kundu, Seokkyun Ko, Chris H. Kim. 1-4 [doi]
- A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFEClifford Ting, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura. 1-4 [doi]
- Design for data-center, low-power and SoCsRick Paul, Aurangzeb Khan. 1 [doi]
- High-performance analog/mixed-signal characterization techniquesDoug Garrity, Brandt Braswell. 1-53 [doi]
- A high gain operational amplifier via an efficient conductance cancellation techniqueBin Huang, Degang Chen. 1-4 [doi]
- Compact modeling of LDMOS working in the third quadrantKejun Xia, Harihara Indana, Usha Gogineni. 1-4 [doi]
- A VCO-based current-to-digital converter for sensor applicationsPraveen Prabha, Seong Joong Kim, Karthikeyan Reddy, Sachin Rao, Nathanael Griesert, Arun Rao, Greg Winter, Pavan Kumar Hanumolu. 1-4 [doi]
- Design Technology co-optimization for N10Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, M. Dusa, Arindam Mallik, S. Sakhare, B. Vandewalle, Piet Wambacq, Bharani Chava, Kris Croes, Morin Dehan, Doyoung Jang, P. Leray, T. T. Liu, Kenichi Miyaguchi, Bertrand Parvais, P. Schuddinck, P. Weemaes, Abdelkarim Mercha, J. Bommels, N. Horiguchi, G. McIntyre, Aaron Thean, Zsolt Tokei, S. Cheng, Diederik Verkest, A. Steegen. 1-8 [doi]
- A multi-phase sub-harmonic injection locking technique for bandwidth extension in silicon-based THz signal generationTaiyun Chi, Jun Luo, Song Hu, Hua Wang. 1-4 [doi]
- Reconfigurable blocker-resilient receiver with concurrent dual-band carrier aggregationRun Chen, Hossein Hashemi. 1-4 [doi]
- A 160 MS/s, 11.1 mW, single-channel pipelined SAR ADC with 68.3 dB SNDRVaibhav Tripathi, Boris Murmann. 1-4 [doi]
- A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOSMing-Shuan Chen, Chih-Kong Ken Yang. 1-4 [doi]
- Power managementWilliam McIntyre, Olivier Trescases. 1 [doi]
- A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew J. Turnquist, Mikko Kaltiokallio. 1-4 [doi]
- TM microprocessorRobert Groves, Phillip Restle, Alan J. Drake, David Shan, Michael Thomson. 1-4 [doi]
- A millimeter-wave tunable transformer-based dual-antenna duplexer with 50 dB isolationChuang Lu, Marion Matters-Kammerer, Reza Mahmoudi, Peter G. M. Baltus. 1-4 [doi]
- Advanced simulation techniquesChenjie Gu, Larry Nagel. 1 [doi]
- Reconfigurable SDR front-end techniquesBram Nauta. 1-103 [doi]
- An open-loop class-D audio amplifier with increased low-distortion output power and PVT-insensitive EMI reductionShih-Hsiung Chien, Li-Te Wu, Ssu-Ying Chen, Ren-Dau Jan, Min-Yung Shih, Ching-Tzung Lin, Tai-Haur Kuo. 1-4 [doi]
- A bidirectional neural interface SoC with an integrated spike recorder, microstimulator, and low-power processor for real-time stimulus artifact rejectionKanokwan Limnuson, Hui Lu, Hillel J. Chiel, Pedram Mohseni. 1-4 [doi]
- A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recoveryJack Kenney, Terry Chen, Larry DeVito, Declan Dalton, Stuart McCracken, Richard Soenneker, Ward S. Titus, Todd S. Weigandt. 1-4 [doi]
- The challenges of analog circuits on nanoscale technologiesGregory F. Taylor. 1-6 [doi]
- A capacitive-coupling technique with phase noise and phase error reduction for multi-phase clock generationFeng Zhao, Fa Foster Dai. 1-4 [doi]
- A fully-integrated, 90% peak efficiency, 0.99 power factor, AC-DC LED Driver with on-chip direct-AC-connect series startup pre-regulatorPercy Neyra, Mohammad A. Al-Shyoukh. 1-4 [doi]
- A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technologyMahdi Elghazali, Manoj Sachdev, Ajoy Opal. 1-4 [doi]
- AMD SOC power management: Improving performance/watt using run-time feedbackWilliam Lloyd Bircher, Sam Naffziger. 1-4 [doi]
- An all-digital PWM-based ΔΣ ADC with an inherently matched multi-bit quantizerWooyoung Jung, Yousof Mortazavi, Brian L. Evans, Arjang Hassibi. 1-4 [doi]
- Miniaturized energy-harvesting piezoelectric chargersGabriel Alfonso Rincón-Mora. 1-18 [doi]
- A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loopSocrates D. Vamvakos, Charles Boecker, Eric Groen, Alvin Wang, Shaishav Desai, Scott Irwin, Vithal Rao, Aldo Bottelli, Jawji Chen, Xiaole Chen, Prashant Choudhary, Kuo-Chiang Hsieh, Paul Jennings, Haidang Lin, Dan Pechiu, Chethan Rao, Jason Yeung. 1-4 [doi]
- An 85-225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOSBo Wu, Yun Chiu. 1-4 [doi]
- Inherently linear time symmetric pulse width modulationYue Hu, Yang Xu, Un-Ku Moon. 1-4 [doi]
- Linear current-controlled oscillator for analog to digital conversionK. R. Raghunandan, T. Lakshmi Viswanathan, Thayamkulangara R. Viswanathan. 1-4 [doi]
- A 14pJ/pulse-TX, 0.18nJ/b-RX, 100Mbps, channelized, IR-UWB transceiver for centimeter-to-meter range biotelemetryA. Ebrazeh, P. Mohseni. 1-4 [doi]
- Low power transceivers and oscillatorsFoster F. Dai, Byunghoo Jung. 1 [doi]
- A 27μW subcutaneous wireless biosensing platform with optical power and data transferKannan A. Sankaragomathi, Luis Perez, Ramin Mirjalili, Babak A. Parviz, Brian P. Otis. 1-4 [doi]
- A hybrid SAR-VCO ΔΣ ADC with first-order noise shapingArindam Sanyal, Kareem Ragab, Long Chen, T. R. Viswanathan, Shouli Yan, Nan Sun. 1-4 [doi]
- Design technology co-optimization for 10 nm and beyondTakamaro Kikkawa, Rajiv V. Joshi. 1 [doi]
- Multi-mode cellular transceivers for LTE and LTE-AdvancedPatrick Rakers, Mohammed Alam, David Newman, Kurt Hausmann, Daniel Schwartz, Mahib Rahman, Mark Kirschenmann. 1-8 [doi]
- CMOS (Sub)-mm-Wave System-on-Chip for exploration of deep space and outer planetary systemsAdrian Tang 0002, Mau-Chung Frank Chang, G. Chattopadhyay, Z. Chen, T. Reck, H. Schone, Y. Zhao, L. Du, D. Murphy, N. Chahat, E. Decrossas, I. Mehdi. 1-4 [doi]
- HTOL SRAM Vmin shift considerations in scaled HKMG technologiesS. Balasubramanian, V. Joshi, T. Klick, R. Mann, J. Versaggi, A. Gautam, C. Weintraub, G. Kurz, G. Krause, A. Kerber, B. Parameshwaran, T. Nigam. 1-4 [doi]
- A 105dBA SNR, 0.0031% THD+N filterless class-D amplifier with discrete time feedback control in 55nm CMOSMartin Kinyua, Ruopeng Wang, Eric G. Soenen. 1-4 [doi]
- A 1.2V 110-MHz-UGB differential class-AB amplifier in 65nm CMOSAkshay Visweswaran, John R. Long, Robert Bogdan Staszewski. 1-4 [doi]
- Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation studyM. Kar, D. Lie, M. Wolf, V. De, S. Mukhopadhyay. 1-4 [doi]
- Lookup-table-based background linearization for VCO-based ADCsJohn A. McNeill, Rabeeh Majidi, Jianping Gong, Chengxin Liu. 1-4 [doi]
- Stochastic testing simulator for integrated circuits and MEMS: Hierarchical and sparse techniquesZheng Zhang, Xiu Yang, Giovanni Marucci, Paolo Maffezzoni, Ibrahim Abe M. Elfadel, George E. Karniadakis, Luca Daniel. 1-8 [doi]
- Analog techniquesJohn McNeill, Mohammad Ranjbar. 1 [doi]
- A methodology for yield-specific leakage estimation in memorySubho Chatterjee, Pramod Kolar, Wei Jian Chan, Jae Y. Ko, Gunjan H. Pandya. 1-4 [doi]
- Challenges for analog nanoscale technologyRamnath Venkatraman, Richard Guo. 1 [doi]
- A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECCAdam Neale, Manoj Sachdev. 1-4 [doi]
- A 0.45mW 12b 12.5MS/s SAR ADC with digital calibrationWei Li, Tao Wang, Jorge A. Grilo, Gabor C. Temes. 1-4 [doi]
- MBus: A 17.5 pJ/bit/chip portable interconnect bus for millimeter-scale sensor systems with 8 nW standby powerYe-Sheng Kuo, Pat Pannuto, Gyouho Kim, Zhiyoong Foo, Inhee Lee, Benjamin P. Kempke, Prabal Dutta, David Blaauw, Yoonmyung Lee. 1-4 [doi]
- 2 inductive transceiver for volume-constrained microsystemsMohammad Hassan Ghaed, Skylar Skrzyniarz, David Blaauw, Dennis Sylvester. 1-4 [doi]
- TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodologyDebajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha. 1-4 [doi]
- A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operationsShouhei Kousai, Kohei Onizuka, Song Hu, Hua Wang, Ali Hajimiri. 1-8 [doi]
- Bio-systems at GigahertzEd Lee, Mourad El-Gamal. 1 [doi]
- High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOSRakesh Kumar Palani, Ramesh Harjani. 1-4 [doi]
- A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operationJoung-Wook Moon, Sung-Geun Kim, Dae Hyun Kwon, Woo-Young Choi. 1-4 [doi]
- Circuit techniques for miniaturized biomedical sensorsInhee Lee, Yejoong Kim, Suyoung Bang, Gyouho Kim, Hyunsoo Ha, Yen-Po Chen, Dongsuk Jeon, SeokHyun Jeong, Wanyeong Jung, Mohammad Hassan Ghaed, Zhiyoong Foo, Yoonmyung Lee, Jae-Yoon Sim, Dennis Sylvester, David Blaauw. 1-7 [doi]
- A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOSMing-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang. 1-4 [doi]
- Low drain voltage S/H type PWM LED current driver for BLU in mobile LCDChangbyung Park, Tae-Hwang Kong, Gyu-Hyeong Cho. 1-4 [doi]
- An analog optimum torque control IC for a 200W wind energy conversion system with over 99% MPPT accuracy, 1.7% THDi and 0.99 power factorPeng-Chang Huang, Wen-Chuen Liu, Yi-Chen Liu, Yeong-Chau Kuo, Tai-Haur Kuo. 1-4 [doi]
- Configurable incremental sigma-delta ADC for DC measure and audio conversionZhengyu Wang, Tay Hui Zheng, Dongtian Lu, Sasi Kumar Arunachalam, Xicheng Jiang. 1-4 [doi]
- The role of translational circuits in RF receiver designBehzad Razavi. 1-8 [doi]
- New System-in-Package (SiP) Integration technologiesDoug C. H. Yu. 1-6 [doi]
- Mixed-signal stochastic computation demonstrated in an image sensor with integrated 2D edge detection and noise filteringDavid Fick, Gyouho Kim, Allan Wang, David Blaauw, Dennis Sylvester. 1-4 [doi]
- A stereo 110 dB multi-rate audio ΔΣ DAC with Class-G headphone driverMin Gyu Kim, Dongtian Lu, Todd Brooks, Young-Ju Kim, Vinay Chandrasekhar, Dale Stubbs, Steven Maughan, Bartomeu Servera Mas, David Yu. 1-4 [doi]
- A 5mW 250MS/s 12-bit synthesized digital to analog converterElnaz Ansari, David D. Wentzloff. 1-4 [doi]
- 2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technologyKangyeop Choo, Sung Jin Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hojin Park. 1-4 [doi]
- Impact of random telegraph noise on CMOS logic circuit reliabilityTakashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera. 1-8 [doi]
- Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceiversJan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult. 1-8 [doi]
- A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOCSang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang. 1-4 [doi]
- A tri-stack buck converter with gate coupling control (GCC) and quasi adaptive dead time control (QADTC)Jun-Han Choi, Sang-Hui Park, Gyu-Hyeong Cho. 1-4 [doi]
- Advances in high-speed continuous-time delta-sigma modulatorsTrevor C. Caldwell, David Alldred, Richard Schreier, Hajime Shibata, Yunzhi Dong. 1-8 [doi]
- Energy-efficient bio-sensing systemsPedram Mohseni, Patrick Chiang. 1 [doi]
- Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technologyHsin-Chieh Chen, Wei-Chung Chen, Ying-Wei Chou, Meng-Wei Chien, Chin-Long Wey, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chao-Cheng Lee. 1-4 [doi]
- Modeling of resistance in FinFET local interconnectNing Lu, Pooja M. Kotecha, Richard A. Wachnik. 1-4 [doi]
- A 127-140GHz injection-locked signal source with 3.5mW peak output power by zero-phase coupled oscillator network in 65nm CMOSYang Shang, Hao Yu, Peng Li, Xiaojun Bi, Minkyu Je. 1-4 [doi]
- Energy-efficient Mixed-mode support vector machine processor with analog Gaussian kernelKyeongryeol Bong, Gyeonghoon Kim, Hoi-Jun Yoo. 1-4 [doi]
- A mm-wave class-E 1-bit power modulatorKunal Datta, Hossein Hashemi. 1-4 [doi]
- A 10mV-input boost converter with inductor peak current control and zero detection for thermoelectric energy harvestingAatmesh Shrivastava, David D. Wentzloff, Benton H. Calhoun. 1-4 [doi]
- Design for test of a mm-Wave ADPLL-based transmitterWanghua Wu, Robert Bogdan Staszewski, John R. Long. 1-8 [doi]
- A 5.8nW, 45ppm/°C on-chip CMOS wake-up timer using a constant charge subtraction schemeSeokhyeon Jeong, Inhee Lee, David Blaauw, Dennis Sylvester. 1-4 [doi]
- A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readoutJi-Wook Kwon, Dong-Hwan Jin, Hyeon-June Kim, Sun-Il Hwang, Min Chul Shin, Jong-Ho Kang, Seung-Tak Ryu. 1-4 [doi]
- Recent developments in RF receiversBehzad Razavi. 1-78 [doi]
- PPV-based modeling and event-driven simulation of injection-locked oscillators in SystemVerilogJaeha Kim, Si-Jung Yang, Ji-Eun Jang. 1-4 [doi]
- Advanced memory topicsToshiaki Kirihata, Dinesh Somasekhar. 1 [doi]
- A unified framework for capacitive series-parallel DC-DC converter designRamesh Harjani, Saurabh Chaubey. 1-8 [doi]
- True Random Number Generator circuits based on single- and multi-phase beat frequency detectionQianying Tang, Bongjin Kim, Yingjie Lao, Keshab K. Parhi, Chris H. Kim. 1-4 [doi]
- SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging dataXiaofei Wang, Weichao Xu, Chris H. Kim. 1-4 [doi]
- An efficiency-enhanced 2.4GHz stacked CMOS power amplifier with mode switching scheme for WLAN applicationsYun Yin, Baoyong Chi, Xiaobao Yu, Wen Jia, Zhihua Wang. 1-4 [doi]
- Amplifiers and filtersEric Naviasky, Ken Suyama. 1 [doi]
- A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number systemBo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu. 1-4 [doi]
- A 16-band channelizer employing harmonic rejection mixers with enhanced image rejectionVineet Singh, Travis Forbes, Wei-Gi Ho, Jaegan Ko, Ranjit Gharpurey. 1-4 [doi]
- Testability and reliability enhancement techniquesMike Li, Gordon Roberts. 1 [doi]
- Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errorsAlex Park, Venkat Narayanan, Keith A. Bowman, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine. 1-4 [doi]
- Sub-session: Data converter techniquesJorge A. Grilo, Xicheng Jiang. 1 [doi]
- A wideband RF receiver with >80 dB harmonic rejection ratioRenzhi Liu, Larry Pileggi, Jeffrey A. Weldon. 1-4 [doi]
- A -115dB PSRR CMOS bandgap reference with a novel voltage self-regulating techniqueYuanming Zhu, Fei Liu, Yajuan Yang, Guocheng Huang, Tao Yin, Haigang Yang. 1-4 [doi]
- A 52% tuning range QVCO with a reduced noise coupling scheme and a minimum FOMT of 196dBc/HzMohammad Elbadry, Sachin Kalia, Ramesh Harjani. 1-4 [doi]
- 85-to-127 GHz CMOS transmitter for rotational spectroscopyNavneet Sharma, Jing Zhang, Qian Zhong, Wooyeol Choi, James P. McMillan, Christopher F. Neese, Frank C. De Lucia, K. O. Kenneth. 1-4 [doi]
- A 33μW/node Duty Cycle Controlled HBC Transceiver system for medical BAN with 64 sensor nodesHyungwoo Lee, Hyunwoo Cho, Hoi-Jun Yoo. 1-8 [doi]
- Understanding the regenerative comparator circuitAsad Abidi, Hao Xu. 1-8 [doi]
- Embedded tutorial: Test and manufacturability for silicon photonics and 3D integrationManoj Sachdev, Tetsuya Iizuka. 1 [doi]
- A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfacesChia-Hung Chen, Yi Zhang, Tao He, Patrick Yin Chiang, Gabor C. Temes. 1-4 [doi]
- A 12.5-Gb/s self-calibrating linear phase detector-based CDR using 0.18μm SiGe BiCMOSJeremy Walker, John G. Kenney, Jesse Bankman, Terry Chen, Steve Harston, Kenneth Lawas, Andrew Lewine, Richard Soenneker, Michael St. Germain, Ward S. Titus, Andrew Y. Wang, Kimo Tam. 1-4 [doi]
- A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoMAnkur Guha Roy, Siladitya Dey, Justin Goins, Kartikeya Mayaram, Terri S. Fiez. 1-4 [doi]
- NEEDS: Moving nanoscience to nanotechnologyMark S. Lundstrom. 1-4 [doi]
- A HomePlugAV SoC in 40nm CMOS technologyKeith Findlater, Adria Bofill, Xavier Revés, Jose Abad. 1-8 [doi]
- Directions in future of SRAM with QDR-WideIO for high performance networking applications and beyondAli Keshavarzi, Dinesh Maheshwari, Derwin Mattos, Ravi Kapre, Sandeep Krishnegowda, Morgan Whately, Sudhir Gopalswamy. 1-6 [doi]
- A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technologyKe Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang. 1-4 [doi]
- An 8GHz first-order frequency synthesizer based on phase interpolation and quadrature frequency detection in 65nm CMOSSaman Saeedi, Azita Emami. 1-4 [doi]
- Advanced modeling and simulation of state-of-the-art high-speed I/O interfacesJaeha Kim. 1-122 [doi]
- An ultra-low power power management unit with -40dB switching-noise-suppression for a 3×3 thermoelectric generator array with 57% maximum end-to-end efficiencyJorge Zarate-Roldan, Salvador Carreon-Bautista, Alfredo Costilla-Reyes, Edgar Sánchez-Sinencio. 1-4 [doi]
- A 65 nm CMOS tunable 0.1-to-1.6 GHz distributed transmission line N-path filter with +10 dBm blocker toleranceChris M. Thomas, Lawrence E. Larson. 1-4 [doi]
- Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOSRinkle Jain, Stephen T. Kim, Vaibhav Vaidya, James Tschanz, Krishnan Ravichandran, Vivek De. 1-4 [doi]
- Independent N and P process monitors for body bias based process corner correctionLawrence T. Clark, David Kidd, Vineet Agrawal, Samuel Leshner, Gokul Krishnan. 1-4 [doi]
- A 239-281GHz Sub-THz imager with 100MHz resolution by CMOS direct-conversion receiver with on-chip circular-polarized SIW antennaYang Shang, Hao Yu, Chang Yang, Yuan Liang, Wei Meng Lim. 1-4 [doi]
- Progress and future challenges of silicon carbide devices for integrated circuitsTsunenobu Kimoto. 1-8 [doi]
- A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptabilityFengwei An, Toshinobu Akazawa, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch. 1-4 [doi]
- A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technologyTimothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman. 1-4 [doi]
- Thermal modeling methodology for efficient system-level thermal analysisCristiano Santos, Pascal Vivet, Gene Matter, Nicolas Peltier, Sylvian Kaiser, Ricardo Augusto da Luz Reis. 1-4 [doi]
- A robust parasitic-insensitive successive approximation capacitance-to-digital converterHesham Omran, Muhammad Arsalan, Khaled N. Salama. 1-4 [doi]
- An energy harvesting 2×2 60GHz transceiver with scalable data rate of 38-to-2450Mb/s for near range communicationMazhareddin Taghivand, Yashar Rajavi, Kamal Aggarwal, Ada S. Y. Poon. 1-4 [doi]
- Highly energy-efficient and quality-tunable inexact FFT acceleratorsLingamneni Avinash, Christian C. Enz, Krishna V. Palem, Christian Piguet. 1-4 [doi]
- A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced DamageWon Ho Choi, Saroj Satapathy, John Keane, Chris H. Kim. 1-4 [doi]
- A 135GHz SiGe transmitter with a dielectric rod antenna-in-package for high EIRP/channel arraysNicholas Saiz, Nemat Dolatsha, Amin Arbabian. 1-4 [doi]
- A 32-Gb/s 9.3-mW CMOS equalizer with 0.73-V supplyAbishek Manian, Behzad Razavi. 1-4 [doi]
- 3 pulsed 33-GHz radio transmitter in 32-nm SOI CMOSJaebin Choi, Eyal Aklimi, Jared Roseman, David Tsai, Harish Krishnaswamy, Kenneth L. Shepard. 1-4 [doi]
- A voltage-scalable 10-b pipelined ADC with current-mode amplifierYunjae Suh, Seungnam Choi, Byungsub Kim, Hong June Park, Jae-Yoon Sim. 1-4 [doi]
- High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVSSudhir S. Kudva, Saurabh Chaubey, Ramesh Harjani. 1-4 [doi]
- 3D multi-gesture sensing system for large areas based on pixel self-capacitance readout using TFT scanning and frequency-conversion circuitsYingzhe Hu, Tiffany Moy, Liechao Huang, Warren Rieutort-Louis, Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma. 1-4 [doi]
- Enabling flexible datacenter interconnect networks with WDM silicon photonicsGregory A. Fish, Daniel K. Sparacin. 1-6 [doi]
- Wireline clocking and equalizationWilliam Walker, Dennis Michael Fischette. 1 [doi]
- Robust, reconfigurable, and power-efficient biosignal recording systemsVaibhav Karkare, Hariprasad Chandrakumar, Dejan Rozgic, Dejan Markovic. 1-8 [doi]
- A 0.18-μm CMOS fully integrated 0.7-6 GHz PLL-based complex dielectric spectroscopy systemOsama Elhadidy, Sherif Shakib, Keith Krenek, Samuel Palermo, Kamran Entesari. 1-4 [doi]
- An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog componentsHao San, Rompei Sugawara, Masao Hotta, Tatsuji Matsuura, Kazuyuki Aihara. 1-4 [doi]
- A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniquesKeunsoo Song, Sangkwon Lee, Dongkyun Kim, Youngbo Shim, Sangil Park, Bokrim Ko, Duckhwa Hong, Yongsuk Joo, Wooyoung Lee, Yongdeok Cho, Wooyeol Shin, Jaewoong Yun, Hyengouk Lee, Jeonghun Lee, Eunryeong Lee, Jaemo Yang, Haekang Jung, Namkyu Jang, Joohwan Cho, Hyeongon Kim. 1-4 [doi]
- A fully integrated electroencephalogram (EEG) analog front-end IC with capacitive input impedance boosting loopSeunghyun Lim, Changho Seok, Hyunho Kim, Haryong Song, Hyoungho Ko. 1-4 [doi]
- A 500nA quiescent current, trim-free, ±1.75% absolute accuracy, CMOS-only voltage reference based on anti-doped N-channel MOSFETsMohammad Al-Shyoukh, Alex Kalnitsky. 1-4 [doi]
- A multiple-output fixed current stimulation ASIC for peripherally-implantable neurostimulation systemEdward K. F. Lee, Eusebiu Matei, Van Gang, Jess Shi, Ali Zadeh. 1-4 [doi]
- A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLANSandipan Kundu, Julia H. Lu, Erkan Alpman, Hasnain Lakdawala, Jeyanandh Paramesh, Byunghoo Jung, Sarit Zur, Eshel Gordon. 1-4 [doi]
- Modeling of advanced devicesColin McAndrew, Hidetoshi Onodera. 1 [doi]
- Virtual de-embedding study for the accurate extraction of Fin FET gate resistanceShireen Warnock, Rob Groves, Hongmei Li, Richard A. Wachnik, Pooja M. Kotecha, Sungjae Lee, Ning Lu, Paul Solomon, Keith Jenkins. 1-4 [doi]
- Robust design and experimental demonstrations of carbon nanotube digital circuitsGage Hills, Max M. Shulaker, Hai Wei, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra. 1-4 [doi]
- Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOSJafar Savoj, Hesam Aslanzadeh, Declan Carey, Marc Erett, Wayne Fang, Yohan Frans, Kenny C.-H. Hsieh, Jay Im, Anup Jose, Didem Turker, Parag Upadhyaya, Daniel Wu, Ken Chang. 1-4 [doi]
- A baseband technique for automated LO leakage suppression achieving > -80dBm in wideband passive mixer-first receiversSuren Jayasuriya, Dong Yang, Alyosha C. Molnar. 1-4 [doi]
- A fully integrated translational tracking filter with >40dB blocker attenuation and >68dB harmonic rejection in 40nm for Digital TV tuner applicationsKun-Da Chu, Ying-Tsang Lu, Chao-Wei Wang, Chih-Ming Hung, Meng-Chang Lee, Shih-Chieh Yen. 1-4 [doi]
- A 45-ratio recursively sliced series-parallel switched-capacitor DC-DC converter achieving 86% efficiencyLoai G. Salem, Patrick P. Mercier. 1-4 [doi]
- Energy scaling in multi-tiered sensing systems through compressive sensingMohammed Shoaib, Jie Liu, Matthai Philipose. 1-8 [doi]
- Efficient per-element distortion contribution analysis via Harmonic Balance adjointsBichen Wu, Jaijeet Roychowdhury. 1-4 [doi]
- POWER8 design methodology innovations for improving productivity and reducing powerMatthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert Franch, Wing Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban. 1-9 [doi]
- Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOSRobert Pawlowski, Joseph Crop, Minki Cho, James Tschanz, Vivek De, Thomas Fairbanks, Heather Quinn, Shekhar Y. Borkar, Patrick Yin Chiang. 1-4 [doi]
- A supply-scalable differential amplifier with pulse-controlled common-mode feedbackChun-Wei Hsu, Peter R. Kinget. 1-4 [doi]
- Technology-design-manufacturing co-optimization for advanced mobile SoCsGeoffrey Yeap. 1-8 [doi]