Klaas Bult - researchr alias

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Viewing Publication 1 - 28 from 28

2020

A Resistive Degeneration Technique for Linearizing Open-Loop AmplifiersMd Shakil Akter, Rohan Sehgal, Klaas Bult. tcas, 67-II(11):2322-2326, 2020. [doi]

2018

2017

A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiersRohan Sehgal, Frank M. L. van der Goes, Klaas Bult. esscirc 2017: 131-134 [doi]

2015

2014

A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibrationRohan Sehgal, Frank M. L. van der Goes, Klaas Bult. esscirc 2014: 67-70 [doi]

A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOSFrank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, Jan Mulder, Sijia Wang, Klaas Bult. jssc, 49(12):2835-2845, 2014. [doi]

11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOSFrank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Jan Mulder, Sijia Wang, Klaas Bult. isscc 2014: 200-201 [doi]

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOSJan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult. isscc 2014: 146-147 [doi]

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceiversJan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult. cicc 2014: 1-8 [doi]

2013

A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOSSilvian Spiridon, Johan van der Tang, Han Yan, Hua-feng Chen, Davide Guermandi, Xiaodong Liu, Erol Arslan, Frank M. L. van der Goes, Klaas Bult. jssc, 48(7):1595-1604, 2013. [doi]

2011

2009

2004

A 21-mW 8-b 125-MSample/s ADC in 0.09-mm/sup 2/ 0.13-/spl mu/m CMOSJan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan R. Westra, Marcel Lugthart, Erol Arslan, Rudy J. van de Plassche, Klaas Bult, Frank M. L. van der Goes. jssc, 39(12):2116-2125, 2004. [doi]

1999

1998

1997

An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm/sup 2/Klaas Bult, Aaron Buchwald. jssc, 32(11):1887-1895, 1997. [doi]

1992

An inherently linear and compact MOST-only current division techniqueKlaas Bult, Govert J. G. M. Geelen. jssc, 27(12):1730-1735, December 1992. [doi]

1990

A fast-settling CMOS op amp for SC circuits with 90-dB DC gainKlaas Bult, Govert J. G. M. Geelen. jssc, 25(6):1379-1384, December 1990. [doi]

1989

Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST modelHans Wallinga, Klaas Bult. jssc, 24(3):672-680, June 1989. [doi]

1988

A CMOS analog continuous-time delay line with adaptive delay-time controlKlaas Bult, Hans Wallinga. jssc, 23(3):759-766, June 1988. [doi]

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