Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera. Impact of random telegraph noise on CMOS logic circuit reliability. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014. pages 1-8, IEEE, 2014. [doi]
Abstract is missing.