Jens Leenstra - researchr alias

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Viewing Publication 1 - 23 from 23

2015

2014

POWER8 design methodology innovations for improving productivity and reducing powerMatthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert Franch, Wing Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban. cicc 2014: 1-9 [doi]

2013

2011

2008

Scan chain clustering for test power reductionMelanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding. dac 2008: 828-833 [doi]

2007

IBM POWER6 accelerators: VMX and DFULee Eisen, John Wesley Ward III, Hans-Werner Tast, Nicolas Mäding, Jens Leenstra, Silvia M. Müller, Christian Jacobi 0002, Jochen Preiss, Eric M. Schwarz, Steven R. Carlough. ibmrd, 51(6):663-684, 2007. [doi]

Efficiency of Low Power Circuit Techniques in a 65 nm SOI-ProcessJoachim Fenkes, Tobias Gemmeke, Jens Leenstra. jolpe, 3(1):54-59, 2007. [doi]

Scan Test Planning for Power ReductionMichael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra. dac 2007: 521-526 [doi]

2006

2005

The vector fixed point unit of the synergistic processor element of the cell architecture processorNicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller. esscirc 2005: 203-206 [doi]

2001

Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testabilityMichael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich. itc 2001: 461-469

A 1.8-GHz instruction window buffer for an out-of-order microprocessor coreJens Leenstra, Jürgen Pille, Antje Müller, Wolfram M. Sauer, Rolf Sautter, Dieter F. Wendel. jssc, 36(11):1628-1635, 2001. [doi]

2000

Custom circuit design as a driver of microprocessor performanceDavid H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel. ibmrd, 44(6):799-822, 2000. [doi]

1997

Hierarchical Random Simulation Approach for the Verification of S/390 CMOS MultiprocessorsJörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile. dac 1997: 89-94 [doi]

1991

Hierarchical Test Program Development for Scan Testable CircuitsJens Leenstra, Lambert Spaanenburg. itc 1991: 375-384

1990

Hierarchical test assembly for macro based VLSI designJens Leenstra, Lambert Spaanenburg. itc 1990: 520-529 [doi]

1989

On the Design and Test of Asynchronous Macros Embedded in Synchronous SystemsJens Leenstra, Lambert Spaanenburg. itc 1989: 838-845

On structured gate forest VLSI designGerhard Roos, Jens Leenstra, Thomas Schwederski, Lambert Spaanenburg, Bernd Höfflinger. jsa, 27(1-5):785-792, 1989. [doi]

Issues in the test of artificial neural networksFrank Warkowski, Jens Leenstra, Jos Nijhuis, Lambert Spaanenburg. iccd 1989: 487-490 [doi]

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