Table of Contents

• Architectures for efficient face authentication in embedded systemsNajwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 1-6 [doi]
• Software implementation of Tate pairing over GF(2:::m:::)Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto, Gerardo Pelosi, L. Sportiello. 7-11 [doi]
• Optimization of regular expression pattern matching circuits on FPGACheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang. 12-17 [doi]
• Satisfiability-based framework for enabling side-channel attacks on cryptographic softwareNachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee. 18-23 [doi]
• An 830mW, 586kbps 1024-bit RSA chip designChingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang. 24-29 [doi]
• Platform independent debug port controller architecture with security protection for multi-processor system-on-chip ICsDmitry Akselrod, Asaf Ashkenazi, Yossi Amon. 30-35 [doi]
• Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround timeFrancisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer. 36-41 [doi]
• Energy-efficient FPGA interconnect designMaurice Meijer, Rohini Krishnan, Martijn T. Bennebroek. 42-47 [doi]
• A new approach to compress the configuration information of programmable devicesMaurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante. 48-51 [doi]
• Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)Javier Davila, Alfonso de Torres, Jose Manuel Sanchez, Marcos Sanchez-Elez, Nader Bagherzadeh, Fredy Rivera. 52-57 [doi]
• Application specific instruction processor based implementation of a GNSS receiver on an FPGAGötz Kappen, Tobias G. Noll. 58-63 [doi]
• A methodology for FPGA to structured-ASIC synthesis and verificationMichael Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo. 64-69 [doi]
• Synthesis of system verilog assertionsSayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti. 70-75 [doi]
• Generating finite state machines from SystemCAli Habibi, Haja Moinudeen, Sofiène Tahar. 76-81 [doi]
• Flexible specification and application of rule-based transformations in an automotive design flowJan-Hendrik Oetjens, Joachim Gerlach, Wolfgang Rosenstiel. 82-87 [doi]
• A mixed-signal verification kit for verification of analogue-digital circuitsGiuseppe Bonfini, Monica Chiavacci, Riccardo Mariani, Egidio Pescari. 88-93 [doi]
• A complete and fully qualified design flow for verification of mixed-signal SoC with embedded flash memoriesPierluigi Daglio. 94-99 [doi]
• Software-friendly HW/SW co-simulation: an industrial case studyJuanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello. 100-105 [doi]
• Modeling and simulation of mobile gateways interacting with wireless sensor networksFranco Fummi, Davide Quaglia, Fabio Ricciato, Maura Turolla. 106-111 [doi]
• A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environmentsVassilis Papaefstathiou, Ioannis Papaefstathiou. 112-117 [doi]
• ASIP architecture for multi-standard wireless terminalsDaniele Lo Iacono, J. Zory, Ettore Messina, N. Piazzese, G. Saia, A. Bettinelli. 118-123 [doi]
• Interconnection framework for high-throughput, flexible LDPC decodersFederico Quaglio, Fabrizio Vacca, Cristiano Castellano, Alberto Tarable, Guido Masera. 124-129 [doi]
• Low cost LDPC decoder for DVB-S2John Dielissen, Andries Hekstra, Vincent Berg. 130-135 [doi]
• 3dID: a low-power, low-cost hand motion capture deviceMichele Sama, Vincenzo Pacella, Elisabetta Farella, Luca Benini, Bruno Riccò. 136-141 [doi]
• Industrially proving the SPIRIT consortium specifications for design chain integrationChristopher K. Lennard, Victor Berman, Saverio Fazzari, Mark Indovina, Cary Ussery, Marino Strik, John Wilson, Olivier Florent, François Rémond, Pierre Bricaud. 142-147 [doi]
• Networks on chips for high-end consumer-electronics TV system architecturesFrits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis. 148-153 [doi]
• Simulation and analysis of network on chip architectures: ring, spidergon and 2D meshLuciano Bononi, Nicola Concer. 154-159 [doi]
• GALS networks on chip: a new solution for asynchronous delay-insensitive linksG. Campobello, M. Castano, C. Ciofi, Daniele Mangano. 160-165 [doi]
• Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific applicationFlorin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya. 166-171 [doi]
• STAX: statistical crosstalk target set compactionShahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer. 172-177 [doi]
• A fast-lock mixed-mode DLL with wide-range operation and multiphase outputsKuo-Hsing Cheng, Yu-lung Lo. 178-182 [doi]
• How OEMs and suppliers can face the network integration challengesKai Richter, Rolf Ernst. 183-188 [doi]
• A practical implementation of the fault-tolerant daisy-chain clock synchronization algorithm on CANFabiano Costa Carvalho, Carlos Eduardo Pereira, Elias Teodoro Silva Jr., Edison Pignaton de Freitas. 189-194 [doi]
• On the verification of automotive protocolsG. Zarri, F. Colucci, F. Dupuis, R. Mariani, M. Pasquariello, G. Risaliti, C. Tibaldi. 195-200 [doi]
• FlexRay transceiver in a 0.35 µm CMOS high-voltage technologyF. Baronti, P. D Abramo, M. Knaipp, R. Minixhofer, Roberto Roncella, Roberto Saletti, M. Schrems, R. Serventi, V. Vescoli. 201-205 [doi]
• Space-efficient FPGA-accelerated collision detection for virtual prototypingAndreas Raabe, Stefan Hochgürtel, Joachim K. Anlauf, Gabriel Zachmann. 206-211 [doi]
• Mixed-signal design of a digital input power amplifier for automotive audio applicationsSergio Saponara, Pierangelo Terreni. 212-216 [doi]
• Automatic systemC design configuration for a faster evaluation of different partitioning alternativesNico Bannow, Karsten Haug, Wolfgang Rosenstiel. 217-218 [doi]
• Multi-sensor configurable platform for automotive applicationsL. Serafini, F. Carrai, T. Ramacciotti, V. Zolesi. 219-220 [doi]
• Design and implementation of a modular and portable IEEE 754 compliant floating-point unitKingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia. 221-226 [doi]
• A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentationSutjipto Arifin, Peter Y. K. Cheung. 227-232 [doi]
• ASIP design and synthesis for non linear filtering in image processingLuca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr. 233-238 [doi]
• A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applicationsChingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang. 239-243 [doi]
• The vector fixed point unit of the synergistic processor element of the cell architecture processorNicolas Mäding, Jens Leenstra, Juergen Pille, R. Sautter, S. Büttner, S. Ehrenreich, W. Haller. 244-248 [doi]
• Design and test of fixed-point multimedia co-processor for mobile applicationsJu-Ho Sohn, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo. 249-253 [doi]