Chingwei Yeh - researchr alias

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Viewing Publication 1 - 41 from 41

2023

2022

A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke PatientsTay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang. aspdac 2022: 7-8 [doi]

2017

Approximate Distributed Arithmetic for Variable-Latency Table LookupYi-Hsuan Ting, Tay-Jyi Lin, Cheng-Chun Chang, Chih-Chien Hu, Chingwei Yeh, Jinn-Shyan Wang. ngcas 2017: 137-140 [doi]

2016

A low complexity edge-preserved image compression algorithm for LCD overdriveChao-Yang Chang, Chung-Hsun Huang, Hui-Fu Chen, Chingwei Yeh, Yuan-Sun Chu, Tay-Jyi Lin. gcce 2016: 1-2 [doi]

Variable-length VLIW encoding for code size reduction in embedded processorsTing-Yu Shyu, Bo Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen. socc 2016: 296-299 [doi]

2014

Maintaining color fidelity for dual-shot HDR imagingChingwei Yeh, Chen-Yao Tsai, Tay-Jyi Lin, Jiun-In Guo. icce-tw 2014: 65-66 [doi]

2013

Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOSJian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang. isscc 2013: 426-427 [doi]

Embedding Repeaters in Silicon IPs for Cross-IP InterconnectionsJinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang. tvlsi, 21(3):597-601, 2013. [doi]

2012

Towards Process Variation-Aware Power GatingChingwei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang. tvlsi, 20(11):1929-1937, 2012. [doi]

2011

2010

Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall DelaysJinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh. ieicet, 93-C(10):1540-1543, 2010. [doi]

Adaptive Pipeline voltage Scaling in High Performance MicroprocessorChang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh. jcsc, 19(8):1817-1834, 2010. [doi]

2008

High-Speed and Low-Power Design Techniques for TCAM MacrosChao-Ching Wang, Jinn-Shyan Wang, Chingwei Yeh. jssc, 43(2):530-540, 2008. [doi]

2007

A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOSJinn-Shyan Wang, Jian-Shiun Chen, Yi-Ming Wang, Chingwei Yeh. isscc 2007: 294-604 [doi]

Reducing Branch Misprediction Penalties Via Adaptive Pipeline ScalingChang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh. hipeac 2007: 105-119 [doi]

2006

Timing driven power gatingDe-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh. dac 2006: 121-124 [doi]

An AND-type match-line scheme for high-performance energy-efficient content addressable memoriesHung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh. jssc, 41(5):1108-1119, 2006. [doi]

Power minimization for dynamic PLAsTzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh. tvlsi, 14(6):616-624, 2006. [doi]

Performance-driven technology mapping with MSG partition and selective gate duplicationChi-Shong Wang, Chingwei Yeh. todaes, 11(4):953-973, 2006. [doi]

Design of STR level converters for SoCs using the multi-island dual-VDD design techniqueJinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu. iscas 2006: [doi]

TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search LinesJinn-Shyan Wang, Chao-Ching Wang, Chingwei Yeh. isscc 2006: 577-586 [doi]

A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applicationsChingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang. date 2006: 239-243 [doi]

An 830mW, 586kbps 1024-bit RSA chip designChingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang. date 2006: 24-29 [doi]

2005

2004

The CMOS carry-forward addersChung-Hsun Huang, Jinn-Shyan Wang, Chingwei Yeh, Chih-Jen Fang. jssc, 39(2):327-336, 2004. [doi]

2001

An adaptive path selection method for delay testingWen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das. tim, 50(5):1109-1118, 2001. [doi]

Analysis and design of high-speed and low-power CMOS PLAsJinn-Shyan Wang, Ching-Rong Chang, Chingwei Yeh. jssc, 36(8):1250-1262, 2001. [doi]

Cell-based layout techniques supporting gate-level voltage scaling for low powerChingwei Yeh, Yin-Shuin Kang. tvlsi, 9(6):983-986, 2001. [doi]

2000

Cell-based layout techniques supporting gate-level voltage scaling for low powerChingwei Yeh, Yin-Shuin Kang. tvlsi, 8(5):629-633, 2000. [doi]

1999

A simulated annealing based method supporting dual supply voltages in standard cell placementChingwei Yeh, Yin-Shuin Kang. iscas 1999: 310-313 [doi]

A cell selection strategy for low power applicationsChingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang. iscas 1999: 416-419 [doi]

Power reduction through iterative gate sizing and voltage scalingChingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone. iscas 1999: 246-249 [doi]

1996

On the integration of partitioning and global routing for rectilinear placement problemsChingwei Yeh, Chi-Shong Wang. tcad, 15(1):83-91, 1996. [doi]

1994

Block-oriented programmable design with switching network interconnectChingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel. tvlsi, 2(1):45-53, 1994. [doi]

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