Table of Contents

• Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasingShu Hokimoto, Tohru Ishihara, Hidetoshi Onodera. 1-6 [doi]
• Tutorial 3A: Bringing cores closer together: The wireless revolution in on-chip communicationPartha Pande, Jürgen Becker. 1-2 [doi]
• Tutorial 1B: Transistors: Past, present and futureGururaj Shamanna, Sao-Jie Chen. 1-2 [doi]
• Tutorial 4B: ADC design - from system architecture to transistor level designBhibhudatta Sahoo, Vishal Saxena, Karan S. Bhatia. 1-4 [doi]
• Tutorial 1A: Design challenges for the Internet of ThingsDanielle Griffith, Karan S. Bhatia. 1-2 [doi]
• Plenary I: The Internet of important thingsEdward A. Lee, Danella Zhao. 1-3 [doi]
• Tutorial 2A: 3D integration - challenges and advantagesMalgorzata Chrzanowska-Jeske, Jürgen Becker. 1-3 [doi]
• Tutorial 2B: CMOS integrated system on a chip for neural interface applicationsJacques Christophe Rudell, Danella Zhao. 1-2 [doi]
• Tutorial 4A: Supply voltage noise and mitigation for real world SoCsVisvesh Sathe, Andrew Marshall. 1-3 [doi]
• Tutorial 3B: The design challenges for self-powered wireless wearable ECG sensor SoCYong Lian, Andrew Marshall. 1-3 [doi]
• Opening keynote: Crashing drones and hijacked cameras: Cybertrust meets cyberphysicalJeannette M. Wing, Danella Zhao. 1-3 [doi]
• Digital LDO modeling for early design space explorationStefan Leitner, Paul West, Chao Lu, Haibo Wang. 7-12 [doi]
• A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibrationDadian Zhou, Claudio Talarico, José Silva-Martínez. 13-17 [doi]
• Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing applicationMing Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang. 18-23 [doi]
• A 12 bit split-array switched capacitor power amplifier in 130nm CMOSZhidong Bai, Dallas Johnson, Ali Azam, Anirban Saha, Wen Yuan, Jeffrey S. Walling. 24-28 [doi]
• Low-jitter all-digital phase-locked loop with novel PFD and high resolution TDC & DCOXiaoying Deng, Yanyan Mo, Xin Lin, Mingcheng Zhu. 29-34 [doi]
• Statistical design attribute identification for FinFET outlier and Silicon-to-SPICE gapHyosig Won, Katsuhiro Shimazu. 35-40 [doi]
• Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulationJose Eduardo Chiarelli Bueno Filho, Jorge Luis Gonzalez Reano, Wang Jiang Chau. 41-46 [doi]
• A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementationNidhi Batra, Shashwat Kaushik, Anil Kumar Gundu, Mohammad S. Hashmi, G. S. Visweswaran, Anuj Grover. 47-51 [doi]
• CATBR-Congestion Aware Traffic Bridging Routing among hierarchical networks-on-chipMingmin Bai, Dan Zhao, Hongyi Wu. 52-57 [doi]
• EDT dynamic bandwidth management (DBM) in SoC testingYu Huang. 58-63 [doi]
• Toward more efficient scan data bandwidth utilization on modern SOCsYan Dong, Grady Giles, Guoliang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood. 64-68 [doi]
• In-field system-health monitoring based on IEEE 1687Farrokh Ghani Zadegan, Dimitar Nikolov, Erik Larsson. 69-74 [doi]
• Novel lightweight FF-APUF design for FPGAChongyan Gu, Yijun Cui, Neil Hanley, Máire O'Neill. 75-80 [doi]
• Efficient VLSI architecture for SAO decoding in 4K Ultra-HD HEVC video codecMihir N. Mody, Niraj Nandan, Hetul Sanghvi. 81-84 [doi]
• Single-ended D flip-flop with implicit scan mux for high performance mobile APMin-Su Kim, Chunghee Kim, Yong-geol Kim, Ah-Reum Kim, Jikyum Kim, Juhyun Kang, Daeseong Lee, Changjun Choi, Ilsuk Suh, Jungyul Pyo, Youngmin Shin, Jae Cheol Son. 91-95 [doi]
• Multi-objective sample preparation algorithm for microfluidic biochips supporting various mixing modelsYung-Chun Lei, Tung-Hsuan Lin, Juinn-Dar Huang. 96-101 [doi]
• A multiplication reduction technique with near-zero approximation for embedded learning in IoT devicesYuxiang Huan, Yifan Qin, Yantian You, Li-Rong Zheng, Zhuo Zou. 102-107 [doi]
• Feature study on a programmable network traffic classifierKeissy Guerra Perez, Xin Yang, Sandra Scott-Hayward, Sakir Sezer. 108-113 [doi]
• Design and ASIC acceleration of cortical algorithm for text recognitionSumon Dey, Paul D. Franzon. 114-119 [doi]
• A 200 MS/s 8-bit Time-based Analog-to-Digital Converter with inherit sample and holdAli H. Hassan, M. Wagih Ismail, Yehea Ismail, Hassan Mostafa. 120-124 [doi]
• A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryptionWeiwei Shi, Chiu-sing Choy. 125-128 [doi]
• Low voltage Flash memory design based on floating gate SOFFETEmeshaw Ashenafi, Azzedin D. Es-Sakhi, Masud H. Chowdhury. 129-132 [doi]
• Hardware implementation of Hierarchical Temporal Memory algorithmWeifu Li, Paul Franzon. 133-138 [doi]
• An early global routing framework for uniform wire distribution in SoCsBapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal. 139-144 [doi]
• SAMi: Self-aware migration approach for congestion reduction in NoC-based MCSoCAmin Rezaei, Masoud Daneshtalab, Dan Zhao, Mehdi Modarressi. 145-150 [doi]
• Modeling and optimization of the bond-wire interface in a Hybrid CMOS-photonic traveling-wave MZM transmitterKehan Zhu, Vishal Saxena, Xinyu Wu. 151-156 [doi]
• A Jitter Cancellation Circuit for High Speed I/O InterfacesAnupjyoti Deka, Mahalingam Nagarajan. 157-162 [doi]
• A CMOS analog front-end for driving a high-speed SAR ADC in low-power ultrasound imaging systemsTaehoon Kim, Han Yang, Sangmin Shin, Hyongmin Lee, Suhwan Kim. 163-168 [doi]
• Behavioral modeling of drain current of an avalanche ISFET near breakdownMohammad M. Uzzal, Payman Zarkesh-Ha, Paul Szauter, Jeremy S. Edwards. 169-173 [doi]
• An ultra-low power voltage-to-time converter (VTC) circuit for low power and low speed applicationsAli H. Hassan, Hassan Mostafa, Tawfik Ismail, S. R. I. Gabran. 178-182 [doi]
• Automated Full Chip SPICE simulations with self-checking assertions for last mile verification & first pass Silicon of mixed signal SoCsGautham S. Harinarayan, Manmohan Rana, Nitin Pant, Manish Bansal, Sarthak Sharma, Nishant Kaundal. 183-188 [doi]
• Analytical noise model for avalanche ISFET sensor suitable for Next Generation SequencingMohammad M. Uzzal, Payman Zarkesh-Ha, Paul Szauter, Jeremy S. Edwards. 189-193 [doi]
• Rotator-based multiplexer network synthesis for field-data extractorsKoki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa. 194-199 [doi]
• A comparator timing assisted SAR ADC technique with reduced conversion cyclesAbhilash Karnatakam Nagabhushana, Haibo Wang. 200-205 [doi]
• Efficient implementation of the AES algorithm for security applicationsShady Mohamed Soliman, Baher Magdy, Mohamed A. Abd El ghany. 206-210 [doi]
• High-voltage low-power startup backup battery switch using low voltage devices in 28nm CMOSFilippo Neri, Craig Keogh, Thomas Brauner, Eric De Mey, Christian Schippel. 211-216 [doi]
• Design of a power-efficient ARM processor with a timing-error detection and correction mechanismSao-Jie Chen, Grace Liu, Hsin-Ping Yang, Cheng-Hao Luo, Wen-mei Hwu. 217-222 [doi]
• Compressive image sensor technique with sparse measurement matrixStefan Leitner, Haibo Wang, Spyros Tragoudas. 223-228 [doi]
• Performance optimization and power efficiency in 3D IC with buffer insertion schemeMohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske. 229-234 [doi]
• CaPSuLe: A camera-based positioning system using learningYongshik Moon, Soonhyun Noh, Daedong Park, Chen Luo, Anshumali Shrivastava, Seongsoo Hong, Krishna Palem. 235-240 [doi]
• Overcoming the power wall by exploiting inexactness and emerging COTS architectural features: Trading precision for improving application qualityMike Fagan, Jeremy Schlachter, Kazutomo Yoshii, Sven Leyffer, Krishna V. Palem, Marc Snir, Stefan M. Wild, Christian C. Enz. 241-246 [doi]
• Low-power real-time intelligent SoCs for smart machinesYouchang Kim, Injoon Hong, Seongwook Park, Hoi-Jun Yoo. 247-252 [doi]
• Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistorsLuhao Wang, Tiansong Cui, Shahin Nazarian, Yanzhi Wang, Massoud Pedram. 253-258 [doi]
• Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuitsDarya Almasi, Houman Homayoun, Hassan Salmani, Hamid Mahmoodi. 259-264 [doi]
• Modeling and simulation of quantum-well infrared photodetectorsSao-Jie Chen, Hsin-Ping Yang, Ding-Jyun Lin, Grace Liu. 265-270 [doi]
• Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technologyMotoi Ichihashi, Jia Zeng, Cole Zemke, Irene Lin, Greg Northrop, Ning Jin, Jongwook Kye. 271-274 [doi]
• A low power fourth order ΣΔ CMOS modulator with subthreshold amplifierSeong Jae Hyeon, Kwang Sub Yoon, Soo Hun Yang. 275-279 [doi]
• A novel design of a Dual Functionality Read-Write driver for SRAMPulkit Sharma, M. S. Hashmi. 280-285 [doi]
• Novel ultra low voltage mobile compatible RF MEMS switch for reconfigurable microstrip antennaMoez El-Massry, Moataz M. Medhat, Hassan Mostafa. 286-289 [doi]
• Heterogeneous memory assembly exploration using a floorplan and interconnect aware frameworkPrakhar Raj Gupta, G. S. Visweswaran, Gaurav Narang, Anuj Grover. 290-295 [doi]
• Variable-length VLIW encoding for code size reduction in embedded processorsTing-Yu Shyu, Bo Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen. 296-299 [doi]
• Self-dual diamond-graph CMOS H-bridge logic familyShun-Wen Cheng. 300-305 [doi]
• ERFAN: Efficient reconfigurable fault-tolerant deflection routing algorithm for 3-D Network-on-ChipSomayeh Maabi, Farshad Safaei, Amin Rezaei, Masoud Daneshtalab, Dan Zhao. 306-311 [doi]
• Design of high-speed low-power polar BP decoder using emerging technologiesAo Ren, Bo Yuan, Yanzhi Wang. 312-316 [doi]
• A low-computation-complexity, energy-efficient, and high-performance linear program solver using memristor crossbarsRuizhe Cai, Ao Ren, Yanzhi Wang, Sucheta Soundarajan, Qinru Qiu, Bo Yuan, Paul Bogdan. 317-322 [doi]
• Efficient hardware architecture of softmax layer in deep neural networkBo Yuan. 323-326 [doi]
• Noisy neuromorphic circuit modeling Obsessive Compulsive DisorderSaeid Barzegarjalali, Kun Yue, Alice C. Parker. 327-332 [doi]
• Practical power consumption analysis with current smartphonesXiang Chen, Kent W. Nixon, Yiran Chen. 333-337 [doi]
• A fully parallel content addressable memory design using multi-bank structureShixiong Jiang, Vijayalakshmi Saravanan, Pengzhan Yan, Ramalingam Sridhar. 338-343 [doi]
• New power budgeting and thermal management scheme for multi-core systems in dark siliconHai Wang, Ming Zhang, Sheldon X.-D. Tan, Chi Zhang, Yuan Yuan, Keheng Huang, Zhenghong Zhang. 344-349 [doi]
• Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviationYi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, Jinn-Shyan Wang. 350-355 [doi]
• Security challenges in mobile and IoT systemsSandip Ray, Jayanta Bhadra. 356-361 [doi]
• Quantifying trust in autonomous system under uncertaintiesRaj Gautam Dutta, Xiaolong Guo, Yier Jin. 362-367 [doi]
• Striking a balance between SoC security and debug requirementsWen Chen, Jayanta Bhadra. 368-373 [doi]