Kwang Sub Yoon - researchr alias

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Viewing Publication 1 - 12 from 12

2018

th-Order Delta-Sigma Modulator with One Reconfigurable AmplifierJae-hyeon Sung, Kwang Sub Yoon. glvlsi 2018: 471-474 [doi]

2016

A low power fourth order ΣΔ CMOS modulator with subthreshold amplifierSeong Jae Hyeon, Kwang Sub Yoon, Soo Hun Yang. socc 2016: 275-279 [doi]

A CMOS buck converter with PFM / hysteretic modeTae-Heon Lee, Jong-Gu Kim, Kwang Sub Yoon. isocc 2016: 347-348 [doi]

A CMOS 10-bit SAR ADC with threshold configuring comparator for 5 MSBsSang-Heon Lee, Seong Jae Hyeon, Kim Jong Gu, Kwang Sub Yoon. isocc 2016: 255-256 [doi]

2014

Design of a low power CMOS 10bit flash-SAR ADCGi-Yoon Lee, Kwang Sub Yoon. socc 2014: 88-91 [doi]

2012

Design of high dimming ratio power-LED driver with preloading inductor current methodologyKeon Lee, Dong-Hun Lee, Su-hun Yang, Ji-hyun Park, Kwang Sub Yoon. isocc 2012: 9-12 [doi]

2011

Design of a 12-b asynchronous SAR CMOS ADCJinwoo Kim, Shin-Il Lim, Kwang Sub Yoon, Sangmin Lee. isocc 2011: 70-72 [doi]

2004

Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal CircuitSoo-Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung-Soo Kim. ismvl 2004: 198-203 [doi]

2003

A dual band CMOS VCO with a balanced duty cycle bufferYun Cheol Han, Kwang il Kim, Jun Kim, Kwang Sub Yoon. glvlsi 2003: 277-280 [doi]

1999

A 3.3 V high speed CMOS PLL with 3-250 MHz input locking rangeHyuk-Jun Sung, Kwang Sub Yoon. iscas 1999: 553-556 [doi]

1996

A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance LoadJai-Sop Hyun, Kwang Sub Yoon. glvlsi 1996: 260 [doi]

1995

A Precision Output Conductance Model for Analog CMOS Circuit SimulationsJong Kug Seon, Kwang Sub Yoon. iscas 1995: 1584-1587

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