Table of Contents

• Loop-List Scheduling for Heterogeneous Functional UnitsYun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi. 2-7 [doi]
• Synthesis of Real-Time Recursive DSP Algorithms Using Multiple ChipsDuen-Jeng Wang, Yu Hen Hu. 8-13 [doi]
• Resource-Constrained Algebraic Transformation for Loop PipeliningJian-Feng Shi, Liang-Fang Chao. 14-17 [doi]
• A Global Mode Instruction Minimization Technique for Embedded DSPsGary William Grewal. 18 [doi]
• A 1.0ns 64-bits GaAs Adder using Quad tree algorithmPhilippe Royannez, Amara Amara. 24-28 [doi]
• FPGA-based high performance page layout segmentationNalini K. Ratha, Anil K. Jain, Diane T. Rover. 29-34 [doi]
• A Reprogrammable FPGA-Based ATM Traffic GeneratorPong P. Chu. 35-38 [doi]
• Software Fault Tolerance Using Dynamically Reconfigurable FPGAsKevin A. Kwiat, Warren Debany, Salim Hariri. 39 [doi]
• A New Faster Algorithm for Iterative Placement ImprovementMoazzem Hossain, Bala Thumma, Sunil Ashtaputre. 44-49 [doi]
• An Accurate Interconnection Length Estimation for Computer LogicDirk Stroobandt, Herwig Van Marck, Jan Van Campenhout. 50-55 [doi]
• A Minimum-Area Floorplanning Algorithm for MBC DesignsDinesh P. Mehta, Naveed A. Sherwani. 56-59 [doi]
• A New Model for General Connectivity and its Application to PlacementJianjian Song, Heng Kek Choo, Wenjun Zhuang. 60 [doi]
• A Parameterized Index-Generator for the Multi-Dimensional Interleaving OptimizationNelson L. Passos, Edwin Hsing-Mean Sha. 66-71 [doi]
• A High Speed VLSI Architecture for Scaleable ATM SwitchesPaul Shipley, Sherif Sayed, Magdy A. Bayoumi. 72-76 [doi]
• A Design Exploration EnvironmentJörg Wilberg, A. Kuth, Raul Camposano, Wolfgang Rosenstiel, Heinrich Theodor Vierhaus. 77-80 [doi]
• A Parametrical Architecture for Reed-Solomon DecodersMariana-Eugenia Petre, Guido Masera. 81 [doi]
• A Provably Good Moat Routing AlgorithmJoseph L. Ganley, James P. Cohoon. 86-85 [doi]
• On Locally Optimal Breaking of Complex Cyclic Vertical Constraints in VLSI Channel RoutingAnthony D. Johnson. 92-95 [doi]
• Chip Pad Migration is a Key Component to High Performance MCM DesignJames Loy, Atul Garg, Mukkai S. Krishnamoorthy, John F. McDonald. 96-99 [doi]
• An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell PlacementJin-Tai Yan. 100 [doi]
• Formal Verification of an ATM Switch Fabric using Multiway Decision GraphsSofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny, Michel Langevin. 106-111 [doi]
• Boolean Function Representation Using Parallel-Access DiagramsValeria Bertacco, Maurizio Damiani. 112-117 [doi]
• Logic Synthesis for TestabilityChien-Chung Tsai, Malgorzata Marek-Sadowska. 118-121 [doi]
• Self-Timed Mesochronous Interconnection for High-Speed VLSI SystemsSeokjin Kim, Ramalingam Sridhar. 122-125 [doi]
• Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDsLaura Heinrich-Litan, Paul Molitor, Dirk Möller. 126 [doi]
• Performance-Driven Interconnect Global RoutingDongsheng Wang, Ernest S. Kuh. 132-136 [doi]
• Recent Developments in Performance Driven Steiner Routing: An OverviewManjit Borah, Robert Michael Owens, Mary Jane Irwin. 137-142 [doi]
• Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing ModelMasato Edahiro, Richard J. Lipton. 143-147 [doi]
• Simultaneous Routing and Buffer Insertion for High Performance InterconnectJohn Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin. 148-153 [doi]
• Timing and Power Optimization by Gate Sizing Considering False PathsGuangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru. 154 [doi]
• Exact Computation of the Entropy of a Logic CircuitEnrico Macii, Massimo Poncino. 162-167 [doi]
• CMOS Transistor Sizing for Minimization of Energy-Delay ProductChristophe Tretz, Charles A. Zukowski. 168-173 [doi]
• Low-Power Implementation of Discrete Cosine TransformEmad N. Farag, Mohamed I. Elmasry. 174-177 [doi]
• Some Issues in Gray Code AddressingHuzefa Mehta, Robert Michael Owens, Mary Jane Irwin. 178-181 [doi]
• A Hierarchal Approach for Power Reduction in VLSI ChipsPrakash Arunachalam, Jacob A. Abraham, Manuel A. d Abreu. 182 [doi]
• TROY: A Tree-Based Approach to Logic Synthesis and Technology MappingWinfried Nöth, Uwe Hinsberger, Reiner Kolla. 188-193 [doi]
• Transistor Chaining in CMOS Leaf Cells of Planar TopologyBradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian. 194-199 [doi]
• Partitioning Algorithms for Corner StitchingMario A. Lopez, Dinesh P. Mehta. 200 [doi]
• Test Generation for Networks of Interacting FSMs Using Symbolic TechniquesFabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto. 208-213 [doi]
• Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS CircuitsSankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya. 214-219 [doi]
• Efficient Delay Test Generation for Modular CircuitsNidhi Agrawal, Parul Agarwal, C. P. Ravikumar. 220 [doi]
• Design and VLSI Implementation of a Unified Synapse-Neuron ArchitectureHormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller. 228-233 [doi]
• Rapid Prototyping for Fuzzy SystemsChantana Chantrapornchai, Sissades Tongsima, Edwin Hsing-Mean Sha. 234-239 [doi]
• A Modular Architecture for Real Time HDTV Motion Estimation with Large Search RangeHangu Yeo, Yu Hen Hu. 240 [doi]
• A VLSI Interconnection Network Router Using a D-CAM with Hidden RefreshJosé G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville. 246-251 [doi]
• A High-Speed, Real-to-Quadrature Converter with Filtering and DecimationL. Desormeaux, V. Szwarc, J. Lodge. 252-255 [doi]
• A CMOS VLSI Implementation of an NxN Multiplexing Circuitry for ATM ApplicationsMaher E. Rizkalla, Richard L. Aldridge, Nadeem A. Khan, Harry C. Gundrum. 256-259 [doi]
• A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance LoadJai-Sop Hyun, Kwang Sub Yoon. 260 [doi]
• Delay Hazards in Complex Gate Based Speed Independent VLSI CircuitsNozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian. 266-271 [doi]
• Macromodeling C- and RC-loaded CMOS inverters for timing analysisAyman I. Kayssi. 272-276 [doi]
• On Verifying the Correctness of Retimed CircuitsShi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen. 277 [doi]
• On Double Transition Faults as a Delay Fault ModelIrith Pomeranz, Sudhakar M. Reddy, Janak H. Patel. 282-287 [doi]
• Improving Circuit Testability by Clock ControlKent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal. 288-293 [doi]
• An Efficient Multiple Scan Chain Testing SchemeZaifu Zhang, Robert D. McLeod. 294 [doi]