Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru. Timing and Power Optimization by Gate Sizing Considering False Paths. In 6th Great Lakes Symposium on VLSI (GLS-VLSI 96), March 22-23, 1996, Ames, IA, USA. pages 154, IEEE Computer Society, 1996. [doi]
Abstract is missing.