C. Y. Roger Chen - researchr alias

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Viewing Publication 1 - 71 from 71

2022

CWcollab: Presenting multimedia with web-based context-aware collaborationChunxu Tang, Beinan Wang, C. Y. Roger Chen, Huijun Wu. entcom, 43:100511, 2022. [doi]

2021

CWcollab: A Context-Aware Web-Based Collaborative Multimedia SystemChunxu Tang, Beinan Wang, C. Y. Roger Chen, Huijun Wu. icc 2021: 1-6 [doi]

2016

Transistor and pin reordering for leakage reduction in CMOS circuitsJae Woong Chun, C. Y. Roger Chen. mj, 53:25-34, 2016. [doi]

2015

Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay ModelJiani Xie, C. Y. Roger Chen. glvlsi 2015: 361-366 [doi]

2012

A tool to generate models based on behavioral IBIS modelsB. S. Deepaksubramanyan, C. Y. Roger Chen, Adrian Nunez. mwscas 2012: 234-237 [doi]

2008

Modeling and reduction of complex timing constraints in high performance digital circuitsVeerapaneni Nagbhushan, C. Y. Roger Chen. iccd 2008: 544-550 [doi]

2007

A technique for selecting CMOS transistor ordersTing Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen. iccd 2007: 438-443 [doi]

An efficient gate delay model for VLSI designTing Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen. iccd 2007: 450-455 [doi]

Algorithms to simplify multi-clock/edge timing constraintsVeerapaneni Nagbhushan, C. Y. Roger Chen. iccd 2007: 444-449 [doi]

2003

Detailed Placement with Net Length ConstraintsBill Halpin, Naresh Sehgal, C. Y. Roger Chen. iwsoc 2003: 22-27 [doi]

A novel ultra-fast heuristic for VLSI CAD steiner treesBharat Krishna, C. Y. Roger Chen, Naresh Sehgal. glvlsi 2003: 192-197 [doi]

2001

Timing Driven Placement using Physical Net ConstraintsBill Halpin, C. Y. Roger Chen, Naresh Sehgal. dac 2001: 780-783 [doi]

2000

1999

Transistor Chaining in Static CMOS Functional Cells of Arbitrary Planar TopologyBradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian. DAM, 90(1-3):89-114, 1999. [doi]

1998

Partitionable multistage interconnection networks. Part 1: Dynamic subcube compactionMuhammad Naeem Ayyaz, Dikran S. Meliksetian, C. Y. Roger Chen. telsys, 10(1):79-106, 1998.

Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing ConsiderationsBharat Krishna, C. Y. Roger Chen, Naresh Sehgal. vlsid 1998: 53-58

1997

Smoothing Algorithms for the Delivery of Compressed VideoTacettin Kiprulu, Dikran S. Meliksetian, C. Y. Roger Chen. icc 1997: 1330-1334

1996

Transistor Chaining in CMOS Leaf Cells of Planar TopologyBradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian. glvlsi 1996: 194-199 [doi]

1995

Dual Eulerian Properties of Plane MultigraphsBradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian. siamdm, 8(1):33-50, 1995. [doi]

A preprocessor for improving channel routing hierarchical pin permutationC. Y. Roger Chen, Cliff Yungchin Hou, Bradley S. Carlson. tcad, 14(7):896-903, 1995. [doi]

A pin permutation algorithm for improving over-the-cell channel routingC. Y. Roger Chen, Cliff Yungchin Hou. tcad, 14(8):1030-1037, 1995. [doi]

A queueing analysis of the performance of DQDBC. Y. Roger Chen, Georges A. Makhoul, Dikran S. Meliksetian. ton, 3(6):872-881, 1995. [doi]

Design of a Multimedia Object-Oriented DBMSC. Y. Roger Chen, Dikran S. Meliksetian, M. C. Chang, L. J. Liu. mms, 3(5-6):217-227, 1995.

A new model for the performance evaluation of synchronous circuit switched multistage interconnection networksC. Y. Roger Chen, Shuo-Hsien Hsiao, Abdulaziz S. Almazyad. ton, 3(6):708-715, 1995. [doi]

Special Issue on Multimedia Processing and TechnologyArif Ghafoor, C. Y. Roger Chen. jpdc, 30(2):107-110, 1995. [doi]

Synthesis of Asynchronous Circuits - Testing Unique Circuit Behavior of Signal Transition GraphsCalvin J. A. Hsia, C. Y. Roger Chen. iscas 1995: 1074-1077

LILA: layout generation for iterative logic arraysQinghong Wu, C. Y. Roger Chen, Bradley S. Carlson. tcad, 14(11):1359-1369, 1995. [doi]

1994

Sequencer-Based Data Path Synthesis of Regular Iterative AlgorithmsMohammed Aloqeely, C. Y. Roger Chen. dac 1994: 155-160 [doi]

A new technique for exploiting regularity in data path synthesisC. Y. Roger Chen, Mohammed Aloqeely. eurodac 1994: 394-399 [doi]

Optimal algorithms for bubble sort based non-Manhattan channel routingC. Y. Roger Chen, Cliff Yungchin Hou, Uminder Singh. tcad, 13(5):603-609, 1994. [doi]

Synthesis of Application-Specific Multiprocessor SystemsMuhammad K. Dhodhi, Imtiaz Ahmad, C. Y. Roger Chen. eurodac 1994: 671

Performance analysis of single-buffered multistage interconnection networksShuo-Hsien Hsiao, C. Y. Roger Chen. tcom, 42(9):2722-2729, 1994. [doi]

An analytical model for partially blocking finite-buffered switching networksJames V. Luciani, C. Y. Roger Chen. ton, 2(5):533-540, 1994. [doi]

Performance Evaluation of HIPPI Interconnection System Using a Camp-On StrategyAbdulaziz S. Mazyad, C. Y. Roger Chen. lcn 1994: 20-29

Multimedia Object Modeling and Storage Allocation StrategiesKingsley C. Nwosu, C. Y. Roger Chen, P. Bruce Berra. jiis, 3(3/4):357-398, 1994.

A High Performance General Purpose Multi-Point Signal RouterNaresh Kumar Seghal, C. Y. Roger Chen, John M. Acken. iscas 1994: 475-478

An object-oriented cell library managerNaresh Sehgal, C. Y. Roger Chen, John M. Acken. iccad 1994: 750-753 [doi]

A gridless multi-layer area routerNaresh Sehgal, C. Y. Roger Chen, John M. Acken. glvlsi 1994: 158-161 [doi]

Efficent Boolean Matching Algorithm for Cell LibrariesQinghong Wu, C. Y. Roger Chen, John M. Acken. iccd 1994: 36-39

1993

Performance Enhancement of CMOS VLSI Circuits by Transistor ReorderingBradley S. Carlson, C. Y. Roger Chen. dac 1993: 361-366 [doi]

Multimedia object modelling and storage allocation strategies for heterogeneous parallel access storage devices in real time multimedia computing systemsC. Y. Roger Chen, Kingsley C. Nwosu, P. Bruce Berra. compsac 1993: 216-223 [doi]

Modeling and Storage Allocation Strategies for Homogeneous Parallel Access Storage Devices in Real Time Multimedia Information ProcessingC. Y. Roger Chen, Kingsley C. Nwosu, P. Bruce Berra. icci 1993: 565-569

A New Model for the Performance Evaluation of Synchronous Circuit Switched Multistage Interconnection NetworksShuo-Hsien Hsiao, C. Y. Roger Chen. ipps 1993: 773-777

Optimal Routing Algorithm and the Diameter of the Cube-Connected CyclesDikran S. Meliksetian, C. Y. Roger Chen. tpds, 4(10):1172-1178, 1993. [doi]

A Markov-Modulated Bernoulli Process Approximation for the Analysis of Banyan NetworksDikran S. Meliksetian, C. Y. Roger Chen. sigmetrics 1993: 183-194

1992

A heuristic for data path synthesis using multiport memoriesImtiaz Ahmad, C. Y. Roger Chen. glvlsi 1992: 44-51 [doi]

Issues in Networking and Data Management of Distributed Multimedia SystemsP. Bruce Berra, C. Y. Roger Chen, Arif Ghafoor, Thomas D. C. Little. hpdc 1992: 4-15

A Pin Permutation Algorithm for Improving Over-the-Cell Channel RoutingCliff Yungchin Hou, C. Y. Roger Chen. dac 1992: 594-599 [doi]

Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold StrategyShuo-Hsien Hsiao, C. Y. Roger Chen. tpds, 3(5):632-640, 1992. [doi]

Performance Analysis of Communications in Static Interconnection NetworksDikran S. Meliksetian, C. Y. Roger Chen. sigmetrics 1992: 249-250

The Signal Flow Model: A novel Data Driven Approach to Parallel ProcessingMuhammad F. Mudawwar, C. Y. Roger Chen. icpp 1992: 196-200

From logic to symbolic layout for gate matrixUminder Singh, C. Y. Roger Chen. tcad, 11(2):216-227, 1992. [doi]

1991

Post-Processor for Data Path Synthesis Using Multiport MemoriesImtiaz Ahmad, C. Y. Roger Chen. iccad 1991: 276-279

Optimal cell generation for dual independent layout stylesBradley S. Carlson, C. Y. Roger Chen, Uminder Singh. tcad, 10(6):770-782, 1991. [doi]

Datapath Scheduling for Two-Level PipeliningC. Y. Roger Chen, Michael Z. Moricz. dac 1991: 603-606 [doi]

A delay distribution methodology for the optimal systolic synthesis of linear recurrence algorithmsC. Y. Roger Chen, Michael Z. Moricz. tcad, 10(6):685-697, 1991. [doi]

A Hierarchical Methodology to Improve Channel Routing by Pin PermutationCliff Yungchin Hou, C. Y. Roger Chen. iccad 1991: 440-443

Performance analysis of single-buffered multistage interconnection networksShuo-Hsien Hsiao, C. Y. Roger Chen. spdp 1991: 864-867 [doi]

Multimedia SynchronizationThomas D. C. Little, C. Y. Roger Chen, C. S. Chang, P. Bruce Berra. DEBU, 14(3):26-35, 1991. [doi]

1990

1989

On a class of (2n-1)-stage rearrangeable interconnection networksCalvin J. A. Hsia, C. Y. Roger Chen. iccd 1989: 452-455 [doi]

1988

TOBOL - a new methodology for the top-to-bottom level hardware description in VLSI design-automation systemsC. Y. Roger Chen. iccl 1988: 404-411 [doi]

A new algorithm for CMOS gate matrix layoutC. Y. Roger Chen, Cliff Yungchin Hou. iccad 1988: 138-141 [doi]

A new layout optimization methodology for CMOS complex gatesC. Y. Roger Chen, Cliff Yungchin Hou. iccad 1988: 368-371 [doi]

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