Abstract is missing.
- Low power and high performance design challenges in future technologiesVivek De, Shekhar Borkar. 1-6 [doi]
- CMOS system-on-a-chip voltage scaling beyond 50nmAzeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl. 7-12 [doi]
- Reducing bus transition activity by limited weight coding with codeword slimmingVijay Sundararajan, Keshab K. Parhi. 13-16 [doi]
- Supporting system-level power exploration for DSP applicationsLuca Benini, Marco Ferrero, Alberto Macii, Enrico Macii, Massimo Poncino. 17-22 [doi]
- Formal hardware verification by integrating HOL and MDGV. K. Pisini, Sofiène Tahar, Paul Curzon, Otmane Aït Mohamed, Xiaoyu Song. 23-28 [doi]
- Towards design and validation of mixed-technology SOCsSalvador Mir, Benoît Charlot, Gabriela Nicolescu, Philippe Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz. 29-33 [doi]
- Candidate subcircuits for functional module identification in logic circuitsJennifer L. White, Anthony S. Wojcik, Moon-Jung Chung, Travis E. Doom. 34-38 [doi]
- Speeding up symbolic model checking by accelerating dynamic variable reorderingChristoph Meinel, Christian Stangier. 39-42 [doi]
- Prove that a faulty multiplier is faulty!?Sandro Wefel, Paul Molitor. 43-46 [doi]
- Manhattan or non-Manhattan?: a study of alternative VLSI routing architecturesCheng-Kok Koh, Patrick H. Madden. 47-52 [doi]
- High-performance bidirectional repeatersSudhakar Bobba, Ibrahim N. Hajj. 53-58 [doi]
- Measuring routing congestion for multi-layer global routingTom Chen, Alkan Cengiz. 59-62 [doi]
- Transparent repeatersRadu M. Secareanu, Eby G. Friedman. 63-66 [doi]
- A wave-pipelined router architecture using ternary associative memoryJosé G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan. 67-70 [doi]
- A novel technique for sea of gates global routingBharat Krishna, C. Y. Roger Chen, Naresh Sehgal. 71-74 [doi]
- On-chip inductance modelingDavid Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang. 75-80 [doi]
- An evolutionary approach to timing driven FPGA placementR. Venkatraman, Lalit M. Patnaik. 81-85 [doi]
- Parallel algorithms for FPGA placementMalay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee. 86-94 [doi]
- Fast and accurate estimation of floorplans in logic/high-level synthesisKia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh. 95-100 [doi]
- A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applicationsGeorge Gristede, Wei Hwang. 101-106 [doi]
- Digital CMOS logic operation in the sub-threshold regionHendrawan Soeleman, Kaushik Roy. 107-112 [doi]
- Low power high speed analog-to-digital converter for wireless communicationsA. E. Hussein, Mohamed I. Elmasry. 113-116 [doi]
- A comparative study of power efficient SRAM designsJeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin. 117-122 [doi]
- Design and analysis of efficient application-specific on-line page replacement techniquesVirgil Andronache, Edwin Hsing-Mean Sha, Nelson L. Passos. 123-128 [doi]
- A new technique for estimating lower bounds on latency for high level synthesisHelvio P. Peixoto, Margarida F. Jacome. 129-132 [doi]
- Maximizing memory data reuse for lower power motion estimationBo-Sung Kim, Jun Dong Cho. 133-138 [doi]
- Efficient algorithms for acceptable design explorationChantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Hu. 139-142 [doi]
- Technology independent arbitrary device extractorQiao Li, Sung-Mo Kang. 143-146 [doi]
- Regression-based RTL power models for controllersLuca Benini, Alessandro Bogliolo, Enrico Macii, Massimo Poncino, Mihai Surmei. 147-152 [doi]
- A low-power correlatorBibhudatta Sahoo, Martin Kuhlmann, Keshab K. Parhi. 153-155 [doi]
- Behavioral-level partitioning for low power design in control-dominated applicationKi-Seok Chung, Taewhan Kim, Chien-Liang Liu. 156-161 [doi]
- Power estimation for a submicron CMOS inverter driving a CRC interconnect loadHung-Jung Chen, Bradley S. Carlson. 162-166 [doi]
- Accuracy management for mixed-mode digital VLSI simulationGary L. Dare, Charles A. Zukowski. 167-170 [doi]
- Noise estimation due to signal activity for capacitively coupled CMOS logic gatesKevin T. Tang, Eby G. Friedman. 171-176 [doi]
- SPARTA: Simulation of Physics on a Real-Time ArchitectureBenjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin. 177-182 [doi]
- Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitchingQiao Li, Sung-Mo Kang. 183-188 [doi]
- MCM placement using a realistic thermal modelCraig Beebe, Jo Dale Carothers, Alfonso Ortega. 189-192 [doi]
- A sensitivity based placer for standard cellsBill Halpin, C. Y. Roger Chen, Naresh Sehgal. 193-196 [doi]