Charles A. Zukowski - researchr alias

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Viewing Publication 1 - 28 from 28

2010

Characteristics of MS-CMOS logic in sub-32nm technologiesKagan Irez, Jiaping Hu, Charles A. Zukowski. glvlsi 2010: 393-396 [doi]

2006

A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS TechnologyAli Bastani, Charles A. Zukowski. isqed 2006: 312-317 [doi]

Monotonic static CMOS tradeoffs in sub-100nm technologiesAli Bastani, Charles A. Zukowski. glvlsi 2006: 278-283 [doi]

2005

Characterization of monotonic static CMOS gates in a 65nm technologyAli Bastani, Charles A. Zukowski. glvlsi 2005: 408-411 [doi]

Characterization of logic circuit techniques and optimization for high-leakage CMOS technologiesPhillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky. integration, 38(3):491-504, 2005. [doi]

2004

Design of superbuffers in sub-100nm CMOS technologies with significant gate leakageAli Bastani, Charles A. Zukowski. glvlsi 2004: 119-122 [doi]

Characterization of logic circuit techniques for high leakage CMOS technologiesPhillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky. glvlsi 2004: 230-235 [doi]

2003

A custom FPGA for the simulation of gene regulatory networksIlias Tagkopoulos, Charles A. Zukowski, German Cavelier, Dimitris Anastassiou. glvlsi 2003: 132-135 [doi]

2000

Accuracy management for mixed-mode digital VLSI simulationGary L. Dare, Charles A. Zukowski. glvlsi 2000: 167-170 [doi]

Application of dynamic power supply scaling in a low-energy ATM interfaceS. Henry Li, Charles A. Zukowski. iscas 2000: 745-748 [doi]

An assessment of on-line engineering design problem presentation strategiesAnthony A. Renshaw, Joshua H. Reibel, Charles A. Zukowski, Katie Penn, Robert O. McClintock, Morton B. Friedman. te, 43(2):83-91, 2000. [doi]

1996

VLSI Design Optimization of Input/Output-Buffered Broadband ATM SwitchesHong Shi, Charles A. Zukowski, Omar Wing. infocom 1996: 810-817

CMOS Transistor Sizing for Minimization of Energy-Delay ProductChristophe Tretz, Charles A. Zukowski. glvlsi 1996: 168-173 [doi]

1995

Buffer size trade-offs in input/output buffered ATM switches under various conditionsHong Shi, Naeem Abbasi, Charles A. Zukowski, Omar Wing. icccn 1995: 258 [doi]

1994

Delay-time bounds and waveform bounds for RLCG ladder networksYing-Wen Bai, Charles A. Zukowski. anss 1994: 23-30 [doi]

Generic Queue Scheduling: Concepts and VLSIPaul Landsberg, Charles A. Zukowski. infocom 1994: 1438-1445

1993

Analysis and Control of Timing Jitter in Digital Logic Arising from Noise Voltage SourcesPerng-Shyong Lin, Charles A. Zukowski. iccd 1993: 352-356

Jitter Due to Signal History in Digital Logic Circuits and Its Control StrategiesPerng-Shyong Lin, Charles A. Zukowski. iscas 1993: 2114-2117

1992

High-speed parallel CRC circuits in VLSITong-Bi Pei, Charles A. Zukowski. tcom, 40(4):653-657, 1992. [doi]

Putting routing tables in siliconTong-Bi Pei, Charles A. Zukowski. network, 6(1):42-50, 1992. [doi]

Implementing a High-Frequency Pattern Generator Based on Combinational MergingCharles A. Zukowski, Ying-Wen Bai. iccd 1992: 81-84

1991

VLSI Implementation of Routing Tables: Tries and CAMsTong-Bi Pei, Charles A. Zukowski. infocom 1991: 515-524

1990

Measuring Error Propagation in Waveform Relaxation AlgorithmsCharles A. Zukowski, George Gristede, Albert E. Ruehli. iccad 1990: 170-173

1988

Continuous Models for Communication Density Constraints on Multiprocessor PerformanceLance A. Glasser, Charles A. Zukowski. TC, 37(6):652-656, 1988.

Variable reduction in MOS timing modelsCharles A. Zukowski, De-Ping Chen. iccd 1988: 124-128 [doi]

A matched-delay CMOS TDM multiplexer cellCharles A. Zukowski, Kevin Shum. iccd 1988: 352-355 [doi]

1986

Relaxing Bounds for Linear RC Mesh CircuitsCharles A. Zukowski. tcad, 5(2):305-312, 1986. [doi]

1985

Integrated-Circuit Logarithmic Arithmetic UnitsJeffrey H. Lang, Charles A. Zukowski, Richard O. LaMaire, Chae H. An. TC, 34(5):475-483, 1985.

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