Abstract is missing.
- Field-Programmable Integrted Circuits - Overview and Future TrendsAbbas El Gamal. 2
- Alpha Architecture: Hardware Implementation and Software Programming ImplicationsDerrick Meyer. 4-5
- High Level Design: A Design Vision for the 90 sAart J. de Geus. 8
- Design and Test - The Next ProblemsGordon D. Robinson. 10
- Trends in Computer-Based Systems EngineeringStephanie White, Mack W. Alford, Brian McCay, David Oliver, Colin Tully, Julian Holtzman, C. Stephen Kuehl, David Owens, Allan Willey. 12-15
- Tutorial on Embedded System DesignWayne Wolf, Ernest Frey. 18-21
- Identification of Single Gate Delay Fault RedundanciesDaniel Brand, Vijay S. Iyengar. 24-28
- Behavioral Synthesis for Easy Testability in Data Path AllocationTien-Chien Lee, Wayne Wolf, Niraj K. Jha, John M. Acken. 29-32
- Fast Minimization of Mixed-Polarity AND/XOR Canonical NetworksMarek A. Perkowski, Laszlo Csanky, Andisheh Sarabi, Ingo Schäfer. 33-36
- Statistical Timing Analysis of Combinational CircuitsSrinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik. 38-43
- Fanin Ordering in Multi-Slot Timing AnalysisLukas P. P. P. van Ginneken. 44-47
- Algorithms for Interface Timing VerificationKenneth L. McMillan, David L. Dill. 48-51
- Designing ASICs for Use with Multichip ModulesJeffery Banker. 54-58
- A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-ScanYervant Zorian. 59-66
- VLSI Design of Modulo Adders/SubtractorsGopal Lakhani. 68-71
- Design of Concurrent Error-Detectable VLSI-Based Array DividersThou-Ho Chen, Liang-Gee Chen, Yi-Shing Chang. 72-75
- A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs TechnologiesErik Brunvand, Nick Michell, Kent F. Smith. 76-80
- Implementing a High-Frequency Pattern Generator Based on Combinational MergingCharles A. Zukowski, Ying-Wen Bai. 81-84
- Routability-Driven Techology Mapping for LookUp-Table-Based FPGAsMartine D. F. Schlag, Jackson Kong, Pak K. Chan. 86-90
- Placement-Based Partitioning for Lookup-Table-Based FPGAsSteven Trimberger, Mon-Ren Chene. 91-94
- Routable Technologie Mapping for LUT FPGAsNarasimha B. Bhat, Dwight D. Hill. 95-98
- Improving FPGA Routing Architectures Using Architecture and CAD InteractionsBenjamin Tseng, Jonathan Rose, Stephen Dean Brown. 99-104
- Arithmetic Error Analysis of a new Reciprocal CellVijay K. Jain, Gibert E. Perez, Earl E. Swartzlander Jr.. 106-109
- Reliable Floating-Point Arithmetic Algorithms for Berger Encoded OperandsJien-Chung Lo. 110-113
- MxN Booth Encoded Multiplier Generator Using Optimized Wallace TreesJalil Fadavi-Ardekani. 114-117
- Modified Booth Algorihtm for High Radix MultiplicationPhilip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.. 118-121
- Design and Implementation of a Robot Control System Using a Unified Hardware-Software Rapid Prototyping FrameworkMani B. Srivastava, Trevor I. Blumenau, Robert W. Brodersen. 124-127
- An Application Specific Processor for a Multi-System Navigation ReceiverEric Aardoom, Paul Stravers. 128-131
- NSC s Digital Answering Machine SolutionOhad Falik, Gideon D. Intrater. 132-137
- An Efficient Logic Emulation SystemMichael Butts, Jon Batcheller, Joseph Varghese. 138-141
- The Future of Embedded System DesignJames H. Aylor, Raul Camposano, Michael A. Schuette, Wayne Wolf, Nam S. Woo. 144-146
- System Level Verification of Large Scale ComputerT. Okabayashi, K. Kubo, Z. Hirose, K. Suzuki. 149-152
- An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay OptimizationJason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen. 154-158
- Technology Mapping via Transformations of Function GraphsShih-Chieh Chang, Malgorzata Marek-Sadowska. 159-162
- Synthesis on Multiplexer-Based F.P.G.A. Using Binary Decision DiagramsT. Besson, H. Bouzouzou, M. Crastes, I. Floricica, Gabriele Saucier. 163-167
- MARVLE: A VLSI Chip for Variable Length Encoding and DecodingAmar Mukherjee, Jeffrey W. Flieder, N. Ranganathan. 170-173
- Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural NetworksBaher Haroun, Elie Torbey. 174-178
- One-Chip System Integration for GSM with the DSP KISS-16V2G. Mahlich, G.-H. Huaman-Bollo, J. Preißner, Johannes Schuck, Hans Sahm, P. Weingart, D. Weinsziehr, J. Yeandel. 179-182
- Interconnect Modeling and Design in High-Speed VLSI/ULSI SystemsSoo-Young Oh, Keh-Jeng Chang, Norman Chang, Ken Lee. 184-189
- Fully Differential Optical Interconnects for High-Speed Digital SystemsC. S. Li, Harald S. Stone, C. M. Olsen. 190-193
- Addressing the Tradeoff Between Standard and Custom ICs in System Level DesignJay K. Adams, Donald E. Thomas. 194-197
- IBM Single Chip RISC Processor (RSC)Charles R. Moore, D. M. Balser, J. S. Muhich, R. E. East. 200-204
- The Architecture of the LR33020 GraphX Processor: A MIPS-RISC Based X-Terminal ControllerSanjay Desai. 205-208
- The T9000 TransputerDavid May, Roger Shepherd, Peter Thompson. 209-212
- Electromagnetic Modeling and Simulation of Electronic PackagesRaj Mittra. 214-217
- Three Dimensional Circuit Oriented Electromagnetic Modeling for VLSI InterconnectsHansruedi Heeb, Albert E. Ruehli, J. Eric Bracken, Ronald A. Rohrer. 218-221
- Time Domain Simulation of Multiconductor Transmission Lines with Frequency-Dependent LossesColin Gordon. 222-228
- Directions in Futrue High End ProcessorsGeorge A. Sai-Halasz. 230-233
- Design and Scaling of BiCMOS CircuitsPrasad Raje. 234-238
- DACCT - Dynamic ACCess Testing of IBM Large SystemsJeffrey I. Alter. 240-244
- Constraint Slving for Test Case GenerationAshok K. Chandra, Vijay S. Iyengar. 245-248
- Archimedes: An Approach to Architecutre-Independent Modeling for High-Level SimulationMiyako Odawara, Kazunori Kuriyama, Tadaaki Bandoh. 249-254
- Concurrent Test Scheduling in Built-In Self-Test EnvironmentChien-In Henry Chen, Joel T. Yuen. 256-259
- BIST Generators for Sequential FaultsShujian Zhang, Rod Byrne, D. Michael Miller. 260-263
- Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test EnvironmentChien-In Henry Chen, Joel T. Yuen, Ji-Der Lee. 264-267
- Delay Models for Verifying Speed-Dependent Asynchronous CircuitsJerry R. Burch. 270-274
- Linear Programming for Optimum Hazard Elimination in Asynchronous CircuitsLuciano Lavagno, Alberto L. Sangiovanni-Vincentelli. 275-278
- Synthesis of Timed Asynchronous CircuitsChris J. Myers, Teresa H. Y. Meng. 279-284
- High-Level Synthesis of Self-Recovering MicroArchitecturesAlex Orailoglu, Ramesh Karri. 286-289
- Estimating Lower-Bound Performance of Schedules Using a Relaxation TechniqueMinjoong Rim, Rajiv Jain. 290-294
- Just in Time SchedulingKarl van Rompaey, Ivo Bolsens, Hugo De Man. 295-300
- NVAX and NVAX + Single-Chip CMOS VAX MicroprocessorsDebra Bernstein, John F. Brown III, Rebecca L. Stamm, G. Michael Uhler. 302-305
- Logical Verification of the NVAX CPU Chip DesignWalker Anderson. 306-309
- Design Methodology and CAD Tools for the NVAX MicroprocessorVictor Peng, Dale R. Donchin, Yao-Tsung Yen. 310-313
- State Assignment Algorithms for Parallel Controller SynthesisJames Pardey, Tomasz Kozlowski, Jonathan Saul, Martin Bolton. 316-319
- Finite State Machine Decomposition Using Multiway PartitioningMaya K. Yajnik, Maciej J. Ciesielski. 320-323
- The Role of Prime Compatibles in the Minimization of Finite State MachinesJune-Kyung Rho, Fabio Somenzi. 324-327
- Sequential Circuit Design Using Synthesis and OptimizationEllen Sentovich, Kanwar Jit Singh, Cho W. Moon, Hamid Savoj, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 328-333
- Dynamic Reordering of Hgh Latency Transactions Using a Modified a MicropipelineArmin Liebchen, Ganesh Gopalakrishnan. 336-340
- Practical Asynchronous Controller DesignSteven M. Nowick, Kenneth Y. Yun, David L. Dill. 341-345
- Synthesis of 3D Asynchronous State MachinesKenneth Y. Yun, David L. Dill, Steven M. Nowick. 346-350
- Register Locking in an Asynchronous MicroprocessorN. C. Paver, P. Day, Stephen B. Furber, Jim D. Garside, J. V. Woods. 351-355
- On Minimizing Hardware Overhead for Pseudoexhaustive Circuit TestabilityDimitrios Kagaris, Fillia Makedon, Spyros Tragoudas. 358-364
- Fault Simulation and Test Generation by Fault Sampling TechniquesSami A. Al-Arian, Musaed A. Al-Kharji. 365-368
- Multiple Input Bridging Fault Detection in CMOS Sequential CircuitsNiraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka. 369-372
- Multiple Fault Detection in CMOS Logic CircuitsDing Lu, Carol Q. Tong. 373-376
- Channel Density Minimization by Pin PermutationYang Cai, D. F. Wong. 378-382
- An Area Minimizer for Floorplans with L-Shaped RegionsYachyang Sun, C. L. Liu. 383-386
- Workload-Driven Floorplanning for MIPS OptimizationPradip Bose, David LaPotin, Gopalakrishnan Vijayan, Sungho Kim. 387-391
- Desktop Wars - The PC Versus the WorkstationNick Tredennick. 394
- On Limitations and Extensions of STG Model for Designing Asynchronous Control CircuitsAlexandre Yakovlev. 396-400
- Analysis of Asynchronous Binary Arbitration on Digital-Transmission-Line BussesShlomo Kipnis. 401-406
- Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine SpecificationsTam Anh Chu. 407-413
- The Message Driven Processor: An Integrated Multicomputer Processing ElementWilliam J. Dally, Andrew A. Chien, Stuart Fiske, Greg Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills. 416-419
- The J-Machine NetworkPeter R. Nuth, William J. Dally. 420-423
- MDP Design Tools and MethodsRichard A. Lethin, William J. Dally. 424-428
- Functional VLSI Design Verification Methodology for the CM-5 Massively Parallel SupercomputerMargaret A. St. Pierre, Shaw-Wen Yang, Dan Cassiday. 430-435
- An IEEE 1149.1 Compliant Testability Architecture with Internal ScanRobert C. Zak Jr., Jeffrey V. Hill. 436-442
- Modeling and Simulation of Design ErrorsSungho Kang, Stephen A. Szygenda. 443-446
- On Relationship Between ITE and BDDWilliam K. C. Lam, Robert K. Brayton. 448-451
- Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and VerificationYung-Te Lai, Sarma Sastry, Massoud Pedram. 452-458
- A Synthesis Algorithm for Two-Level XOR Based CircuitsMark A. Heap, William A. Rogers, M. Ray Mercer. 459-463
- SYCLOP: Synthesis of CMOS Logic for Low Power ApplicationsKaushik Roy, Sharat Prasad. 464-467
- Delay Prediction for Technology-Independent Logic EquationsPaul T. Gutwin, Patrick C. McGeer, Robert K. Brayton. 468-471
- Library Mapping of CMOS-Switch-Level-Circuits by Extraction of Isomorphic SubgraphsUrsula Westerholz, Heinrich Theodor Vierhaus. 472-475
- A New Approach to Fault-Tolerance in Linear Analog Systems Based on Checksum-Coded State Space RepresentationsAbhijit Chatterjee. 478-481
- Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space ExpansionXiaodong Xie, Alexander Albicki, Andrzej Krasniewski. 482-485
- Theory and Design of Two-Rail Totally Self-Checking Basic Building BlocksZhi-Jian Jiang, R. Venkatesen. 486-489
- The ETCA Data-Flow Functional Computer for Real-Time Image ProcessingGeorges Quénot, Bertrand Zavidovique. 492-495
- FPGA and Rapid Prototyping Technology Use in a Special Purpose Computer for Molecular GeneticsBarry S. Fagin, J. Gill Watt. 496-501
- The Selective Extra-Stage ButterflySmaragda Konstantinidou. 502-506
- Distributed VLSI Simulation on a Network of WorkstationsSankaran Karthik, Jacob A. Abraham. 508-511
- Hierarchical Simulation of MOS Circuits Using Extracted Functional ModelsJalal A. Wehbeh, Daniel G. Saab. 512-515
- AC++ Based Environment for Analog Circuit SimulationBob Melville, Peter Feldmann, Shahriar Moinian. 516-519
- Protocol Verification as a Hardware Design AidDavid L. Dill, Andreas J. Drexler, Alan J. Hu, C. Han Yang. 522-525
- Verification of I/O Trace Set Inclusion for a Class of Non-Deterministic Finite State MachinesEduard Cerny. 526-530
- The Formal Definition of a Synchronous Hardware-Description Language in Higher Order LogicAndrew D. Gordon. 531-534
- High-Level State Machine Specification and SynthesisAndreas Kuehlmann, Reinaldo A. Bergamaschi. 536-539
- Versioning and Concurrency Control in a Distributed Design EnvironmentAtsushi Takahara. 540-543
- ProperCAd: A Portable Object-Oriented Parallel Environment for VLSI CADBalkrishna Ramkumar, Prithviraj Banerjee. 544-548
- Sampling of Cache Congruence ClassesLishing Liu, Jih-Kwon Peir. 552-557
- A CRegs Implementation Study Based on the MIPS-X RISC ProcessorSteve Nowakowski, Matthew T. O Keefe. 558-563
- ALMP: A Shifting Memory Architecture for Loop PipeliningH. Fatih Ugurdag, Christos A. Papachristou. 564-568
- A Tool for Automatic Generation of BISTed and Transparent BISTed RamsO. Kebichi, Michael Nicolaidis. 570-575
- An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-RepairingTom Chen, Glen Sunada. 576-581
- Repair of RAMs With Clustered FaultsBapiraju Vinnakota, Jason Andrews. 582-585
- Comparing Layouts with HDL Models: A Formal Verification TechniqueTimothy Kam, P. A. Subrahmanyam. 588-591
- RTL Design Verification by Making Use of Datapath InformationMasahiro Fujita. 592-597
- Some Techniques for Efficient Symbolic Simulation-Based VerificationPrabhat Jain, Ganesh Gopalakrishnan. 598-602