Yuzheng Ding - researchr alias

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Viewing Publication 1 - 19 from 19

2005

The effect of post-layout pin permutation on timingYuzheng Ding, Peter Suaris, Nan-Chi Chou. fpga 2005: 41-50 [doi]

2004

Incremental physical resynthesis for timing optimizationPeter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou. fpga 2004: 99-108 [doi]

1999

Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping SolutionJason Cong, Chang Wu, Yuzheng Ding. fpga 1999: 29-35 [doi]

1996

RASP: A General Logic Synthesis System for SRAM-Based FPGAsJason Cong, John Peck, Yuzheng Ding. fpga 1996: 137-143 [doi]

Combinational logic synthesis for LUT based field programmable gate arraysJason Cong, Yuzheng Ding. todaes, 1(2):145-204, 1996. [doi]

1995

On Nominal Delay Minimization in LUT-based FPGA Technology MappingJason Cong, Yuzheng Ding. fpga 1995: 82-88 [doi]

1994

On nominal delay minimization in LUT-based FPGA technology mappingJason Cong, Yuzheng Ding. integration, 18(1):73-94, 1994. [doi]

On area/depth trade-off in LUT-based FPGA technology mappingJason Cong, Yuzheng Ding. tvlsi, 2(2):137-148, 1994. [doi]

FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designsJason Cong, Yuzheng Ding. tcad, 13(1):1-12, 1994. [doi]

LUT-based FPGA technology mapping under arbitrary net-delay modelsJason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen. cg, 18(4):507-516, 1994. [doi]

On the Complexity of Building an Interval HeapYuzheng Ding, Mark Allen Weiss. ipl, 50(3):143-144, 1994.

1993

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designsJason Cong, Yuzheng Ding. iccad 1993: 110-114 [doi]

On Area/Depth Trade-off in LUT-Based FPGA Technology MappingJason Cong, Yuzheng Ding. dac 1993: 213-218 [doi]

The K-D Heap: An Efficient Multi-dimensional Priority QueueYuzheng Ding, Mark Allen Weiss. wads 1993: 302-313

The Relaxed min-max HeapYuzheng Ding, Mark Allen Weiss. ACTA, 30(3):215-231, 1993.

1992

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