Table of Contents

• Using bus-based connections to improve field-programmable gate array density for implementing datapath circuitsAndy Gean Ye, Jonathan Rose. 3-13 [doi]
• The Stratix II logic and routing architectureDavid M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose. 14-20 [doi]
• HARP: hard-wired routing pattern FPGAsSatish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh. 21-29 [doi]
• Skew-programmable clock design for FPGA and skew-aware placementChao-Yang Yeh, Malgorzata Marek-Sadowska. 33-40 [doi]
• The effect of post-layout pin permutation on timingYuzheng Ding, Peter Suaris, Nan-Chi Chou. 41-50 [doi]
• Simultaneous timing-driven placement and duplicationGang Chen, Jason Cong. 51-59 [doi]
• Sparse Matrix-Vector multiplication on FPGAsLing Zhuo, Viktor K. Prasanna. 63-74 [doi]
• Floating-point sparse matrix-vector multiply for FPGAsMichael DeLorimier, André DeHon. 75-85 [doi]
• 64-bit floating-point FPGA matrix multiplicationYong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev. 86-95 [doi]
• Instruction set extension with shadow registers for configurable processorsJason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang. 99-106 [doi]
• An FPGA-based VLIW processor with custom hardware executionAlex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster. 107-117 [doi]
• Techniques for synthesizing binaries to an advanced register/memory structureGreg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid. 118-124 [doi]
• Design of programmable interconnect for sublithographic programmable logic arraysAndré DeHon. 127-137 [doi]
• Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAsNicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko. 138-148 [doi]
• Soft error rate estimation and mitigation for SRAM-based FPGAsGhazanfar Asadi, Mehdi Baradaran Tahoori. 149-160 [doi]
• Automated synthesis for asynchronous FPGAsSong Peng, David Fang, John Teifel, Rajit Manohar. 163-173 [doi]
• Efficient static timing analysis and applications using edge masksMike Hutton, David Karchmer, Bryan Archell, Jason Govig. 174-183 [doi]
• Evaluating heuristics in automatically mapping multi-loop applications to FPGAsHeidi E. Ziegler, Mary W. Hall. 184-195 [doi]
• Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmabilityYan Lin, Fei Li, Lei He. 199-207 [doi]
• Combining low-leakage techniques for FPGA routing designAndrea Lodi 0002, Luca Ciccarelli, Roberto Giansante. 208-214 [doi]
• Design, layout and verification of an FPGA using automated toolsIan Kuon, Aaron Egier, Jonathan Rose. 215-226 [doi]
• Hyper customized processors for bio-sequence database scanning on FPGAsTimothy F. Oliver, Bertil Schmidt, Douglas L. Maskell. 229-237 [doi]
• Efficient packet classification for network intrusion detection using FPGAHaoyu Song, John W. Lockwood. 238-245 [doi]
• CUSP: a modular framework for high speed network applications on FPGAsGraham Schelle, Dirk Grunwald. 246-257 [doi]
• A petri-net based Pre-runtime scheduler for dynamically self-reconfiguration of FPGAs (abstract only)Remy Eskinazi Sant Anna, Manoel Eusebio de Lima, Paulo Romero Martins Maciel, Carlos A. Valderrama, Abel Guilhermino S. Filho, Paulo Sérgio B. do Nascimento. 262 [doi]
• Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only)Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl. 262 [doi]
• 3D FPGAs: placement, routing, and architecture evaluation (abstract only)Cristinel Ababei, Hushrav Mogal, Kia Bazargan. 263 [doi]
• VPart: an automatic partitioning tool for dynamic reconfiguration (abstract only)Leos Kafka, Rafal Kielbik, Rudolf Matousek, Juan Manuel Moreno. 263 [doi]
• A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only)Yirong OuYang, Jiarong Tong. 263 [doi]
• Efficient utilization of heterogeneous routing resources for FPGAs (abstract only)Deepak Rautela, Rajendra S. Katti. 264 [doi]
• Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only)Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel. 264 [doi]
• Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only)E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan. 265 [doi]
• Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluationYohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano. 265 [doi]
• Routing algorithms: enhancing routability & enabling ECO (abstract only)Taraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh. 266 [doi]
• Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only)Akshay Sharma, Carl Ebeling, Scott Hauck. 266 [doi]
• An execution environment for reconfigurable computing (abstract only)Wenyin Fu, Katherine Compton. 267 [doi]
• A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only)Hassan Hassan, Mohab Anis, Mohamed I. Elmasry. 267 [doi]
• Exploration of heterogeneous reconfigurable architectures (abstract only)Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. 268 [doi]
• Energy-efficient FPGA interconnect architecture design (abstract only)Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume. 268 [doi]
• Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only)Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi. 269 [doi]
• Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only)Wen Yujie, Jiarong Tong, Charles Chiang. 269 [doi]
• Dynamic hardware multiplexing for coarse grain reconfigurable architecturesPascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon. 270 [doi]
• 3D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only)Chul Kim, A. M. Rassau, Mike Myung-Ok Lee. 270 [doi]
• Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only)Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers. 271 [doi]
• Soft multiprocessor systems for network applications (abstract only)Yujia Jin, William Plishker, Kaushik Ravindran, Nadathur Satish, Kurt Keutzer. 271 [doi]
• Hierarchical LUT structures for leakage power reduction (abstract only)Somsubhra Mondal, Seda Ogrenci Memik, Debasish Das. 272 [doi]
• Dual-Vt FPGA design for leakage power reduction (abstract only)Akhilesh Kumar, Mohab Anis. 272 [doi]
• SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only)Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee. 273 [doi]
• Configurable hardware solutions for computing autocorrelation coefficients: a case study (abstract only)Jacqueline E. Rice, Kenneth B. Kent, Troy Ronda, Zhao Yong. 274 [doi]
• Dynamic reconfiguration in FPGA-based SoC designs (abstract only)Roman Bartosinski, Martin Danek, Petr Honzík, Rudolf Matousek. 274 [doi]
• Design and implementation of packet classification with FPGA (abstract only)Wang Yong-gang, Yan Tian-xin. 275 [doi]
• A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only)Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusebio de Lima, Remy Eskinazi Sant Anna, Abel Guilhermino S. Filho. 275 [doi]
• Image processing library for reconfigurable computers (abstract only)Mohamed Taher, Esam El-Araby, Tarek A. El-Ghazawi, Kris Gaj. 276 [doi]
• A 2005 review of FPGA arithmetic (abstract only)Stéphane Simard, Rachid Beguenane, Éric Larouche, Luc Morin. 276 [doi]
• Rapid prototyping of a test harness for forward error correcting codes (abstract only)Edward Brown, James Irvine, Bill Wilkie. 276 [doi]
• A framework for rule processing in reconfigurable network systems (abstract only)Michael Attig, John W. Lockwood. 277 [doi]
• An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only)Sven Heithecker, Rolf Ernst. 277 [doi]
• Reconfigurable computers: an empirical analysis (abstract only)Tarek A. El-Ghazawi, Kris Gaj, Nikitas A. Alexandridis, Allen Michalski, Osman Devrim Fidanci, Mohamed Taher, Esam El-Araby, Esmail Chitalwala, Proshanta Saha. 278 [doi]
• A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only)Edward D. Moreno, Fábio Dacêncio Pereira, Rodolfo B. Chiaramonte. 278 [doi]
• An integrated framework for the high level design of high performance signal processing circuits on FPGAs (abstract only)Khaled Benkrid, S. Belkacemi. 278 [doi]
• Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only)Bryan C. Catanzaro, Brent E. Nelson. 279 [doi]
• Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only)Jianchun Li, Christos A. Papachristou, Raj Shekhar. 279 [doi]
• An FPGA generator for multipoint distributed random variables (abstract only)Nicola Bruti Liberati, Eckhard Platen, Filippo Martini, Massimo Piccardi. 280 [doi]
• A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only)Bo Yang, Nikhil Joshi, Ramesh Karri. 280 [doi]