Table of Contents

• The SFRA: a corner-turn FPGA architectureNicholas Weaver, John R. Hauser, John Wawrzynek. 3-12 [doi]
• Exploration of pipelined FPGA interconnect structuresAkshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck. 13-22 [doi]
• Evaluation of low-leakage design techniques for field programmable gate arraysArifur Rahman, Vijay Polavarapuv. 23-30 [doi]
• Active leakage power optimization for FPGAsJason Helge Anderson, Farid N. Najm, Tim Tuan. 33-41 [doi]
• Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabricsFei Li, Yan Lin, Lei He, Jason Cong. 42-50 [doi]
• Reducing leakage energy in FPGAs using region-constrained placementAman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan. 51-58 [doi]
• A high performance 32-bit ALU for programmable logicPaul Metzgen. 61-70 [doi]
• An embedded true random number generator for FPGAsPaul Kohlbrenner, Kris Gaj. 71-78 [doi]
• Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress reportSergio López-Buedo, Eduardo I. Boemo. 79-86 [doi]
• A synthesis oriented omniscient manual editorTomasz S. Czajkowski, Jonathan Rose. 89-98 [doi]
• Incremental physical resynthesis for timing optimizationPeter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou. 99-108 [doi]
• Low-power technology mapping for FPGA architectures with dual supply voltagesDeming Chen, Jason Cong, Fei Li, Lei He. 109-117 [doi]
• What is the right model for programming and using modern FPGAs?André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica. 119 [doi]
• Nanowire-based sublithographic programmable logic arraysAndré DeHon, Michael J. Wilson. 123-132 [doi]
• Highly pipelined asynchronous FPGAsJohn Teifel, Rajit Manohar. 133-142 [doi]
• A magnetoelectronic macrocell employing reconfigurable threshold logicSteve Ferrera, Nicholas P. Carter. 143-151 [doi]
• Flexibility measurement of domain-specific reconfigurable hardwareKatherine Compton, Scott Hauck. 155-161 [doi]
• A quantitative analysis of the speedup factors of FPGAs over processorsZhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers. 162-170 [doi]
• FPGAs vs. CPUs: trends in peak floating-point performanceKeith D. Underwood. 171-180 [doi]
• Application-specific instruction generation for configurable processor architecturesJason Cong, Yiping Fan, Guoling Han, Zhiru Zhang. 183-189 [doi]
• Using reconfigurability to achieve real-time profiling for hardware/software codesignLesley Shannon, Paul Chow. 190-199 [doi]
• A reconfigurable unit for a clustered programmable-reconfigurable processorRichard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter. 200-209 [doi]
• An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithmWang Chen, Panos Kosmas, Miriam Leeser, Carey Rappaport. 213-222 [doi]
• Time and area efficient pattern matching on FPGAsZachary K. Baker, Viktor K. Prasanna. 223-232 [doi]
• A compiled accelerator for biological cell signaling simulationsJohn F. Keane, Christopher Bradley, Carl Ebeling. 233-241 [doi]
• An FPGA implementation of block truncation coding for gray and color imagesSherif M. Saif, Hazem M. Abbas, Salwa M. Nassar. 245 [doi]
• An FPGA implementation of bene permutation networksAnatole D. Ruslanov, Jeremy R. Johnson. 245 [doi]
• Subframe multiplexing for FPGA manufacturing test configurationErik Chmelar. 245 [doi]
• A flexible hardware architecture for 2-D discrete wavelet transformRichard Carbone, Andreas E. Savakis. 246 [doi]
• Routing architecture for multi-context FPGAsAndrea Lodi 0002, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Mario Toma, Fabio Campi. 246 [doi]
• A VHDL MPEG-7 shape descriptor extractorBret Woz, Andreas E. Savakis. 246 [doi]
• Buffer schemes for runtime reconfiguration of function variants in communication systemsHelmut Steckenbiller, Rudi Knorr. 247 [doi]
• Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 triggerChristian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller. 247 [doi]
• Hardware co-simulation in system generator of the AES-128 encryption algorithmDaniel Denning, Malachy Devlin, James Irvine. 247 [doi]
• High-speed systolic array for gene matchingGabriel Caffarena, Slobodan Bojanic, Juan A. López, Carlos E. Pedreira, Octavio Nieto-Taladriz. 248 [doi]
• FPGA-based implementation of single-precision exponential unitChristopher C. Doss, Robert L. Riley Jr.. 248 [doi]
• The gigahertz FPGA: design consideration and applicationsJong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald. 248 [doi]
• Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAsIan Kuon, Aaron Egier, Jonathan Rose. 249 [doi]
• High level area, delay and power estimation for FPGAsTianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee. 249 [doi]
• Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplierJae-Jin Lee, Gi-Yong Song. 249 [doi]
• SPFD-based one-to-many rewiringKatsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi. 250 [doi]
• Addressing application integrity attacks using a reconfigurable architectureJoseph Zambreno, Rahul Simha, Alok N. Choudhary. 250 [doi]
• Fast adders in modern FPGAsJianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris. 250 [doi]
• FPGA modelling for high-performance algorithmsMartin Danek, Josef Kolar. 251 [doi]
• Least-significant bit optimization techniques for FPGAsMark L. Chang, Scott Hauck. 251 [doi]
• SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysisA. Manoj Kumar, B. Jayaram, V. Kamakoti. 251 [doi]
• Improving the reliability of FPGA circuits using triple-modular redundancy (TMR) & efficient voter placementMichael J. Wirthlin. 252 [doi]
• A novel coarse-grain reconfigurable data-path for accelerating DSP kernelsMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis. 252 [doi]
• A constraints programming approach to communication scheduling on SoPC architecturesChristophe Wolinski, Krzysztof Kuchcinski, Maya Gokhale. 252 [doi]
• An FPGA prototype for the experimental evaluation of a multizone network cachePaul Berube, José Nelson Amaral, Mike MacGregor. 253 [doi]
• Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resourcesNavaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis. 253 [doi]
• FPGA-based supercomputing: an implementation for molecular dynamicsIan Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow. 253 [doi]
• An algorithmic approach by heuristics to dynamical reconfiguration of logic resources on reconfigurable FPGAsPhan C. Vinh, Jonathan P. Bowen. 254 [doi]
• Dynamically reconfigurable architecture for high-throughput processing of data centric applicationsMagesh Sadasivam, Sangjin Hong. 254 [doi]
• FPGA implementation of a high speed network interface card for optical burst switched networksPronita Mehrotra, Mrugendra Singhai, Mike Pratt, Mark Cassada, Patrick Hamilton. 255 [doi]
• Low energy FPGA interconnect designRohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek. 255 [doi]
• In-system FPGA prototyping of an itanium microarchitectureRoland E. Wunderlich, James C. Hoe. 255 [doi]
• Online placement infrastructure to support run-time reconfigurationBrian Leonard, Jeff Young, Ron Sass. 256 [doi]
• Automatic discovery, selection, and specialization of modules in RCADERanjesh G. Jaganathan, Matthew Simpson, Ron Sass. 256 [doi]
• An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA designSanghamitra Roy, Debjit Sinha, Prithviraj Banerjee. 256 [doi]
• Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularityTakashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike. 257 [doi]
• Roving testing using new built-in-self-tester designs for FPGAsVinay Verma, Shantanu Dutt. 257 [doi]
• Divide and concatenate: a scalable hardware architecture for universal MACBo Yang, Ramesh Karri, David A. McGrew. 258 [doi]
• On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANsThilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner. 258 [doi]
• A left-edge algorithm approach for scheduling and allocation of hardware contexts in dynamically reconfigurable architecturesRemy Eskinazi Sant Anna, Manoel Eusebio de Lima, Paulo Romero Martins Maciel. 259 [doi]
• Power analysis and estimation tool integrated with XPOWERElias Todorovich, Eduardo I. Boemo, F. Cardells, Javier Valls. 259 [doi]
• Implementation of elliptic curve cryptosystems over GF(2:::n:::) in optimal normal basis on a reconfigurable computerSashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi. 259 [doi]