Ahmad Darabiha - researchr alias

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Viewing Publication 1 - 9 from 9

2008

Power Reduction Techniques for LDPC DecodersAhmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang. jssc, 43(8):1835-1845, 2008. [doi]

Block-Interlaced LDPC Decoders With Reduced Interconnect ComplexityAhmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang. tcas, 55-II(1):74-78, 2008. [doi]

2007

A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOSAhmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang. cicc 2007: 459-462 [doi]

2006

Reconfigurable hardware implementation of a phase-correlation stereoalgorithmAhmad Darabiha, W. James MacLean, Jonathan Rose. mva, 17(2):116-132, 2006. [doi]

A bit-serial approximate min-sum LDPC decoder and FPGA implementationAhmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang. iscas 2006: [doi]

2005

Multi-Gbit/sec low density parity check decoders with reduced interconnect complexityAhmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang. iscas 2005: 5194-5197 [doi]

2004

Reconfigurable Molecular Dynamics SimulatorNavid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow. fccm 2004: 197-206 [doi]

FPGA-based supercomputing: an implementation for molecular dynamicsIan Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow. fpga 2004: 253 [doi]

2003

Video-Rate Stereo Depth Measurement on Programmable HardwareAhmad Darabiha, Jonathan Rose, W. James MacLean. cvpr 2003: 203-210 [doi]

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