Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang. A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007. pages 459-462, IEEE, 2007. [doi]
Abstract is missing.