Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang. A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007. pages 459-462, IEEE, 2007. [doi]
@inproceedings{DarabihaCK07,
title = {A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS},
author = {Ahmad Darabiha and Anthony Chan Carusone and Frank R. Kschischang},
year = {2007},
doi = {10.1109/CICC.2007.4405773},
url = {http://dx.doi.org/10.1109/CICC.2007.4405773},
researchr = {https://researchr.org/publication/DarabihaCK07},
cites = {0},
citedby = {0},
pages = {459-462},
booktitle = {Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007},
publisher = {IEEE},
isbn = {978-1-4244-1623-3},
}