A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS - researchr publication authors

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Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang. A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007. pages 459-462, IEEE, 2007. [doi]

This author has not been identified. Look up 'Ahmad Darabiha' in GoogleThis author has not been identified. Look up 'Anthony Chan Carusone' in GoogleThis author has not been identified. Look up 'Frank R. Kschischang' in Google

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