Table of Contents

• 3D Capacitive Interconnections for High Speed Interchip CommunicationRoberto Canegallo, Alberto Fazzi, Luca Ciccarelli, Luca Magagni, Federico Natali, Pier Luigi Rolandi, Erik Jung, Léa Di Cioccio, Roberto Guerrieri. 1-8 [doi]
• Low-Jitter Active Deskewing Through Injection-Locked Resonant ClockingZheng Xu, Kenneth L. Shepard. 9-12 [doi]
• Wideband Inductive-coupling Interface for High-performance Portable SystemHiroki Ishikuro, Noriyuki Miura, Tadahiro Kuroda. 13-20 [doi]
• A 550ps Access-Time Compilable SRAM in 65nm CMOS TechnologyLarry Wissel, Harold Pilo, Chris LeBlanc, Xiaopeng Wang, Steve Lamphier, Michael Fragano. 21-24 [doi]
• A Disturb Decoupled Column Select 8T SRAM CellVinod Ramadurai, Rajiv V. Joshi, Rouwaida Kanj. 25-28 [doi]
• Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAMJiajing Wang, Benton H. Calhoun. 29-32 [doi]
• Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based TechnologyShin-ichi O'Uchi, Meishoku Masahara, Kunihiro Sakamoto, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki. 33-36 [doi]
• Simple Statistical Analysis Techniques to Determine Minimum Sense Amp Set TimesRobert M. Houle. 37-40 [doi]
• PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETsWeimin Wu, Xin Li, Gennady Gildenblat, Glen O. Workman, Surya Veeraraghavan, Colin C. McAndrew, Ronald van Langevelde, Geert D. J. Smit, Andries J. Scholten, Dick B. M. Klaassen, Josef Watts. 41-48 [doi]
• Charge-Based Compact Modeling of Multiple-Gate MOSFETBenjamín Iñíguez, Antonio Lázaro, Hamdy Abd El Hamid, Oana Moldovan, Bogdan Nae, Jaume Roig, David Jiménez. 49-56 [doi]
• Characterization, Modeling and Extraction of Cu Wire Resistance for 65 nm TechnologyNing Lu, Matthew Angyal, Gerald Matusiewicz, Vincent J. McGahay, Theodorus E. Standaert. 57-60 [doi]
• A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double samplingTakaya Yamamoto, Masumi Kasahara, Tatsuji Matsuura. 61-64 [doi]
• A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDRKentaro Yamamoto, Anthony Chan Carusone, Francis P. Dawson. 65-68 [doi]
• A 94dB SFDR 78dB DR 2.2MHz BW Multi-bit Delta-Sigma Modulator with Noise Shaping DACAlex Jianzhong Chen, Yong Ping Xu. 69-72 [doi]
• A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applicationsXueFeng Chen, Yan Wang, Yoshihisa Fujimoto, Pascal Lo Ré, Yusuke Kanazawa, Jesper Steensgaard, Gabor C. Temes. 73-76 [doi]
• Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog ImperfectionsJian-Yi Wu, Raj Subramoniam, Zhenyong Zhang, Ali Djabbari, Peter Holloway, Franco Maloberti, Masood Yousefi, Mehmat Aslan, Hua Hong, Ahmad Bahai. 77-80 [doi]
• Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and CamcordersJason C. Chen, Chun-Fu Shen, Shao-Yi Chien. 81-84 [doi]
• CAD Techniques for Power Optimization in Virtex-5 FPGAsSubodh Gupta, Jason Helge Anderson, Linda Farragher, Qiang Wang. 85-88 [doi]
• Flash-based Field Programmable Gate Array Technology with Deep Trench IsolationKyung Joon Han, Nigel Chan, Sungrae Kim, Ben Leung, Volker Hecht, Brian Cronquist, Danny Shum, Armin Tilke, Laura Pescini, Martin Stiftinger, Ronald Kakoschke. 89-91 [doi]
• Analysis of Data Remanence in a 90nm FPGATim Tuan, Tom Strader, Steve Trimberger. 93-96 [doi]
• Notice of Violation of IEEE Publication PrinciplesA Single-Conversion SiGe BiCMOS Satellite TV LNB Front-End Using an Image Reject Mixer and a Calibrated Full-Rate VCOA. Maxim, M. Gheorghe, D. Smith. 97-100 [doi]
• A Low Power, High Performance BiCMOS MIMO/Diversity Direct Conversion Transceiver IC for WiBro/WiMAX (802.16e)Matthias Locher, Mark Tomesen, Jeroen Kuenen, Anton Daanen, Henk Visser, Bert Essink, Peter Paul Vervoort, Manjo Nijrolder, Rob Kopmeiners, William Redman-White, Richard A. H. Balmford, Rachid El Waffaoui. 101-105 [doi]
• A Low-IF CMOS Simultaneous GPS Receiver Integrated in a Multimode TransceiverYang Xu, Kevin Wang, Tim Pals, Aristotele Hadjichristos, Kamal Sahota, Charles Persico. 107-110 [doi]
• Single-Chip UHF RFID reader in 0.18- μm CMOSW. Wang, Shuzuo Lou, K. Chui, S. Rong, C. F. Lok, H. Zheng, H. T. Chan, Adam S. W. Man, Howard C. Luong, Vincent Kin Nang Lau, C. Y. Tsui. 111-114 [doi]
• A Versatile Integrated Circuit for the Acquisition of BiopotentialsReid R. Harrison. 115-122 [doi]
• A Spectral-Scanning Magnetic Resonance Imaging (MRI) Integrated SystemArjang Hassibi, Aydin Babakhani, Ali Hajimiri. 123-126 [doi]
• A Real-Time Feedback Controlled Hearing Aid Chip with Reference Ear ModelSunyoung Kim, Seungjin Lee, Namjun Cho, Seong-Jun Song, Hoi-Jun Yoo. 127-130 [doi]
• Multi-functional Monolithic-MEMS Tactile Imager Using Flexible Deformation of Silicon ICHidekuni Takao, Masaki Yawata, Ryo Kodama, Kazuaki Sawada, Makoto Ishida. 131-134 [doi]
• Testing SerDes beyond 4 Gbps - changing prioritiesStephen K. Sunter, Aubin Roy. 135-138 [doi]
• Challenges and Solutions for Standards-Based Serial 10 Gb/s Backplane EthernetAdam Healey. 139-144 [doi]
• 2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory DeviceKazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu. 145-148 [doi]
• Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/OsHossein Sarbishaei, Oleg Semenov, Manoj Sachdev. 149-152 [doi]
• Embedded Test Features for High-Speed Serial I/OJeff Rearick. 153-156 [doi]
• On-Chip Circuit for Measuring Period Jitter and Skew of Clock Distribution NetworksKeith A. Jenkins, Kenneth L. Shepard, Zheng Xu. 157-160 [doi]
• Mismatch-Tolerant Circuit for On-Chip Measurements of Data JitterKiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma. 161-164 [doi]
• A 0.18 μm CMOS Capacitive Detection Lab-on-ChipEbrahim Ghafar-Zadeh, Mohamad Sawan. 165-172 [doi]
• A 400MHz RF Transceiver for Implantable Biomedical Micro-StimulatorsEdward K. Lee, Phil Hess, John Gord, Howard Stover, Patrick Nercessian. 173-176 [doi]
• A Monolithic Bandpass Amplifier for Neural Signal Processing with 25-Hz Low-Frequency CutoffParas Samsukha, Steven L. Garverick. 177-180 [doi]
• A Low Power Carbon Nanotube Chemical Sensor SystemTaeg Sang Cho, Kyeong-Jae Lee, Jing Kong, Anantha P. Chandrakasan. 181-184 [doi]
• A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADCYoung-Ju Kim, Hee-Cheol Choi, Si-Wook Yoo, Seung-Hoon Lee, Dae-Young Chung, Kyoung-Ho Moon, Ho-Jin Park, Jae-Whui Kim. 185-188 [doi]
• 20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS ProcessPratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik. 189-192 [doi]
• A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM Pilot Tone CalibrationYangjin Oh, Boris Murmann. 193-196 [doi]
• A Fourth Order Elliptic Low-Pass Filter with Wide Range of Programmable Bandwidth, Using Four Identical IntegratorsBehzad Saeidi. 197-200 [doi]
• An Idle-Tone Free Dynamic Element Matching AlgorithmMarc Keppler, Donald Thelen. 201-204 [doi]
• A 65-dB DR 1-MHz BW 110-MHz IF bandpass ΣΔ modulator employing electromechanical loop filterRui Yu, Yong Ping Xu. 205-208 [doi]
• A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital DomainN. Yoshii, K. Mizutani, Y. Sugimoto. 209-212 [doi]
• A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOSYing-Zu Lin, Yen-Ting Liu, Soon-Jyh Chang. 213-216 [doi]
• A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK ReceiverYi-Chung Chen, Yi-Chang Wu, Po-Chiun Huang. 217-220 [doi]
• Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital ProcessDavid E. Duarte, George Geannopoulos, Usman Mughal, Keng L. Wong, Greg Taylor. 221-224 [doi]
• Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read StabilitySayeed A. Badrudduza, Lawrence T. Clark. 225-228 [doi]
• Rapid Estimation of the Probability of SRAM Failure due to MOS Threshold VariationsShweta Srivastava, Jaijeet S. Roychowdhury. 229-232 [doi]
• A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing SchemeToshikazu Suzuki, Hiroyuki Yamauchi, Katsuji Satomi, Hironori Akamatsu. 233-236 [doi]
• Dynamic Data Stability in Low-power SRAM DesignMohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev. 237-240 [doi]
• An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance ImprovementTae-Hyoung Kim, Jason Liu, Chris H. Kim. 241-244 [doi]
• Solution to ESD Induced Pocket Isolation Failure in Multi Well CMOSTroy Ruud, Bryce Rasmussen, Bruce Greenwood, Matthew Tyler. 245-248 [doi]
• Integration of CMP Modeling in RC Extraction and Timing FlowHongmei Liao, Li Song, Nickhil Jakatdar, Riko Radojcic. 249-252 [doi]
• Integrated Inductor Actively Engaging Metal Filling RulesJeong-Il Kim, Daeik D. Kim, Jonghae Kim, Choongyeun Cho, Byunghoo Jung, Dimitrios Peroulis. 253-256 [doi]
• A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOSDavid Levacq, Takuya Minakawa, Makoto Takamiya, Takayasu Sakurai. 257-260 [doi]
• Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct WritingAkihiro Nakamura, Masahide Kawaharazaki, Masaya Yoshikawa, Takeshi Fujino. 261-264 [doi]
• Receiver Offset Cancellation in 90-nm PLD Integrated SERDESSimar Maangat, Toan Nguyen, Wilson Wong, Sergey Shumarayev, Tina Tran, Tim Hoang, Richard Cliff. 265-267 [doi]
• Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoCVincent von Kaenel, Toshinari Takayanagi. 269-272 [doi]
• A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaverCheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu. T. Su. 273-276 [doi]
• A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data RecoveryThomas Suttorp, Ulrich Langmann. 277-280 [doi]
• A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDRJaejin Park, J. F. Liu, L. Richard Carley, C. Patrick Yue. 281-284 [doi]
• A 10Gb/s Equalizer with Decision Feedback for High Speed Serial LinksAli Kiaei, Babak Matinpour, Ahmad Bahai, Thomas H. Lee. 285-288 [doi]
• Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet SystemChi-Shiung Lin, Yu-Chun Lin, Shyh-Jye Jou, Mun-Tian Shiou. 289-292 [doi]
• A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN DetectorWei-Zen Chen, Shih Hao Huang. 293-296 [doi]
• A New Spread Spectrum Clock Generator for SATA Using Double Modulation SchemesYi-Bin Hsieh, Yao-Huang Kao. 297-300 [doi]
• An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip InterconnectsVishak Venkatraman, Wayne P. Burleson. 301-304 [doi]
• A 0.6GHz to 2GHz Digital PLL with Wide Tracking RangeVolodymyr Kratyuk, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon. 305-308 [doi]
• A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance ClockingLin Zhang, Berkehan Ciftcioglu, Hui Wu. 309-312 [doi]
• 2 Pipelined ADC with On-Chip Digital Self-CalibrationHo-Young Lee, Tae-Hwan Oh, Ho-Jin Park, Hae-Seung Lee, Mark Spaeth, Jae-Whui Kim. 313-316 [doi]
• A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without CalibrationJ. Li, Robert Leboeuf, Matthew Courcy, Gabriele Manganaro. 317-320 [doi]
• Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS TechniqueYoun-Jae Kook, Jipeng Li, Bumha Lee, Un-Ku Moon. 321-324 [doi]
• A 1V 10b 30MSPS Switched-RC Pipelined ADCGil-Cho Ahn, Min Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon. 325-328 [doi]
• A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDRSimon M. Louwsma, Ed van Tuijl, Maarten Vertregt, Bram Nauta. 329-332 [doi]
• A 43 mW single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOSSamad Sheikhaei, Shahriar Mirabbasi, André Ivanov. 333-336 [doi]
• A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOSIvan Bogue, Michael P. Flynn. 337-340 [doi]
• A Sample-Time Error Compensation Technique for Time-Interleaved ADC SystemsAfshin Haftbaradaran, Kenneth W. Martin. 341-344 [doi]
• Low-jitter and Large-EMI-reduction Spread-spectrum Clock Generator with Auto-calibration for Serial-ATA ApplicationsTakashi Kawamoto, Tomoaki Takahashi, Hiromitsu Inada, Takayuki Noto. 345-348 [doi]
• Wide Lock-Range, Low Phase-Noise PLL using Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency LinearizationHiroshi Kodama, Hiroyuki Okada, Hiromu Ishikawa, Akio Tanaka. 349-352 [doi]
• A 3.2Gb/s Oversampling CDR with Improved Jitter ToleranceMerrick Brownlee, Pavan Kumar Hanumolu, Un-Ku Moon. 353-356 [doi]
• th rate Dual Pulse Ring OscillatorSander L. J. Gierkink. 357-360 [doi]
• Digitally-Enhanced Phase-Locking CircuitsPavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon, Kartikeya Mayaram. 361-368 [doi]
• A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-TimeMoo-young Kim, Dongsuk Shin, Hyunsoo Chae, Sunghwa Ok, Chulwoo Kim. 369-372 [doi]
• An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR InterfaceJun-Hyun Bae, Jin-Ho Seo, Hwan-Seok Yeo, Jae-Whui Kim, Jae-Yoon Sim, Hong June Park. 373-376 [doi]
• A low noise buck converter with a fully integrated continuous time ΣΔ modulated feedback controllerMarnie Wong, Bertan Bakkaloglu, Sayfe Kiaei. 377-380 [doi]
• A compact pulse-based charge pump in 0.13 μm CMOSJeremy Holleman, Brian P. Otis, Chris Diorio. 381-384 [doi]
• An Efficiency-Enhanced Integrated CMOS Rectifier with Comparator-Controlled Switches for Transcutaneous Powered ImplantsSong Guo, Hoi Lee. 385-388 [doi]
• Integrated Regulation for Energy-Efficient Digital CircuitsElad Alon, Mark Horowitz. 389-392 [doi]
• An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge ControlRaymond E. Barnett, Jin Liu. 393-396 [doi]
• A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systemsYu-Shiang Lin, Dennis Sylvester, David Blaauw. 397-400 [doi]
• CMOS-Based MEMS Mirror Driver for Maskless Lithography SystemsJaesik Lee, Joseph Weiner, Hsin-Hung Chen, Yves Baeyens, Vladimir Aksyuk, Young-Kai Chen. 401-404 [doi]
• Reliability Trends with Advanced CMOS Scaling and The Implications for DesignJ. W. McPherson. 405-412 [doi]
• Evolution of CMOS Technology at 32 nm and BeyondGhavam G. Shahidi. 413-416 [doi]
• High-K/Metal Gate Technology: A New HorizonMukesh Khare. 417-420 [doi]
• Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale SystemsMuhannad S. Bakir, Bing Dang, James D. Meindl. 421-428 [doi]
• Reverse Engineering in the Semiconductor IndustryRandy Torrance, Dick James. 429-436 [doi]
• Cochlear Implant Signal Processing ICsBrett A. Swanson, Erika Van Baelen, Mark Janssens, Michael Goorevich, Tony Nygard, Koen Van Herck. 437-442 [doi]
• An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing MemoryDonghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Hoi-Jun Yoo. 443-446 [doi]
• A cost-effective digital front-end realization for 20-bit ΣΔ DAC in 0.13 μm CMOSRun Chen, Liyuan Liu, Dongmei Li. 447-450 [doi]
• A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communicationFlavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner. 451-454 [doi]
• A High-Throughput Maximum a posteriori Probability DetectorRuwan N. S. Ratnayake, Aleksandar Kavcic, Gu-Yeon Wei. 455-458 [doi]
• A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOSAhmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang. 459-462 [doi]
• A heterodyne phase locked loop with GHz acquisition range for coherent locking of semiconductor lasers in 0.13 μm CMOSFirooz Aflatouni, Omeed Momeni, Hossein Hashemi. 463-466 [doi]
• A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/AmplifiersDeyi Pi, Byung-Kwan Chun, Payam Heydari. 467-470 [doi]
• Towards a sub-2.5V, 100-Gb/s Serial TransceiverSorin P. Voinigescu, Ricardo Andres Aroca, Timothy O. Dickson, Sean T. Nicolson, Theodoros Chalvatzis, Pascal Chevalier, Patrice Garcia, Christophe Gamier, Bernard Sautreuil. 471-478 [doi]
• Future Microprocessor Interfaces: Analysis, Design and OptimizationBryan Casper, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Mozhgan Mansuri. 479-486 [doi]
• Time-Variant Characterization and Compensation of Wideband CircuitsAmir Amirkhany, Ali-Azam Abbasfar, Jafar Savoj, Mark A. Horowitz. 487-490 [doi]
• High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant ApplicationsMoon-Jung Kim, Henrik Icking, Harald Gossner, Thomas H. Lee. 491-494 [doi]
• PSP-Based Scalable MOS Varactor ModelJames Victory, Zeqin Zhu, Q. Zhou, Weimin Wu, Gennady Gildenblat, Zhixin Yan, Juan Cordovez, Colin C. McAndrew, F. Anderson, Jeroen C. J. Paasschens, Ronald van Langevelde, P. Kolev, R. Cherne, C. Yao. 495-502 [doi]
• An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETsBertrand Parvais, S. Hu, Morin Dehan, Abdelkarim Mercha, Stefaan Decoutere. 503-506 [doi]
• Synthesis of Optimal On-Chip BalunsSharad Kapur, David E. Long, Robert C. Frye, Yu-Chia Chen, Ming-Hsiang Cho, Huai-wen Chang, Jun-Hong Ou, Bigchoug Hung. 507-510 [doi]
• An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS TechnologyWenping Wang, Vijay Reddy, Anand T. Krishnan, Rakesh Vattikonda, Srikanth Krishnan, Yu Cao. 511-514 [doi]
• Mismatch Characterization of Ring OscillatorsAjay Balankutty, T. C. Chih, C. Y. Chen, Peter R. Kinget. 515-518 [doi]
• The Advanced Compact MOSFET (ACM) Model for Circuit Analysis and DesignCarlos Galup-Montoro, Márcio Cherem Schneider, Ana Isabela Araújo Cunha, Fernando Rangel de Sousa, Hamilton Klimach, Osmar Franca Siebel. 519-526 [doi]
• A 3.5mW 900MHz Down-converter with Multiband Feedback and Device Transconductance ReuseJunghwan Han, Ranjit Gharpurey. 527-530 [doi]
• A Highly Linear Broadband Variable Gain LNA for TV ApplicationsDanilo Manstretta, Leonard Dauphinee. 531-534 [doi]
• A Current-Equalized Distributed Receiver Front-End for UWB Direct Conversion ReceiversAminghasem Safarian, Lei Zhou, Payam Heydari. 535-538 [doi]
• A 65 μW, 1.9 GHz RF to digital baseband wakeup receiver for wireless sensor nodesNathan Pletcher, Simone Gambini, Jan M. Rabaey. 539-542 [doi]
• A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOSJingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski. 543-546 [doi]
• A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse LoopTing Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon. 547-550 [doi]
• A 1.7-GHz 31dBm differential CMOS Class-E Power Amplifier with 58% PAERiccardo Brama, Luca Larcher, Andrea Mazzanti, Francesco Svelto. 551-554 [doi]
• A 2.4GHz Efficiency-Enhanced Rectifier for Wireless TelemetryKe-Hou Chen, Jian-Hao Lu, Shen-Iuan Liu. 555-558 [doi]
• Comparative Studies of Common Control Schemes for Reference Tracking and Application of End-point PredictionYing Wu, Philip K. T. Mok. 559-562 [doi]
• An Ultra-Low-Power Power Management IC for Wireless Sensor NodesMichael D. Seeman, Seth R. Sanders, Jan M. Rabaey. 567-570 [doi]
• A Low Standby Power Flip-flop with Reduced Circuit and Control ComplexityLawrence T. Clark, Mohammed Kabir, Jonathan E. Knudsen. 571-574 [doi]
• A 610-MHz FIR Filter Using Rotary Clock TechniqueZhengtao Yu 0002, Xun Liu. 575-578 [doi]
• A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics SystemsChang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim. 579-582 [doi]
• A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive LatchesVisvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou. 583-586 [doi]
• Addressing Parametric Impact of Systematic Pattern Variations in Digital IC DesignPei-Hua Wang, Brian Lee, Gus Han, Richard Rouse, Philippe Hurat, Nishath Verghese. 587-590 [doi]
• Design Considerations and Benefits of Three-Dimensional Ternary Content Addressable MemoryEun Chu Oh, Paul D. Franzon. 591-594 [doi]
• A 37 ppm/°C Temperature Compensated CMOS ASIC with ±16 V Supply Protection for Capacitive MicroaccelerometersHyoungho Ko, Ahra Lee, Taedong Ahn, Seung Joon Paik, Byoung-Doo Choi, Dong-Il Cho. 595-598 [doi]
• A 500MHz Low Phase-Noise A1N-on-Silicon Reference OscillatorHossein Miri Lavasani, Reza Abdolvand, Farrokh Ayazi. 599-602 [doi]
• 1.1 TMACS/mW Load-Balanced Resonant Charge-Recycling Array ProcessorRafal Karakiewicz, Roman Genov, Gert Cauwenberghs. 603-606 [doi]
• Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal frontsJun Zou, Helmut Graeb, Daniel Mueller, Ulf Schlichtmann. 607-610 [doi]
• Obtaining Frequency Sensitivities to Variations Analytically from Parameterized Nonlinear Oscillator Phase MacromodelsZhichun Wang, Jaijeet S. Roychowdhury. 611-614 [doi]
• Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform DevicesThierry Devoivre, Richard Rouse, Nishath Verghese, Philippe Hurat. 615-618 [doi]
• Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect UtilizationRasit Onur Topaloglu. 619-622 [doi]
• FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso AreaDheepa Lekshmanan, Aditya Bansal, Kaushik Roy. 623-626 [doi]
• A Comprehensive Phase-Transfer Model for Delay-Locked LoopsJames R. Burnham, Gu-Yeon Wei, Chih-Kong Ken Yang, Haitham A. Hindi. 627-630 [doi]
• Efficient Frequency-Domain Simulation of Massive Clock Meshes Using Parallel Harmonic BalanceWei Dong, Peng Li, Xiaoji Ye. 631-634 [doi]
• Low-Voltage Multi-Mode Gm-C Channel Selection Filter for Mobile ApplicationsTien-Yu Lo, Chung-Chih Hung. 635-638 [doi]
• Multi-Mode Modulator and Frequency Demodulator Circuits for Gb/s Data Rate 60 GHz Wireless TransceiversAlberto Valdes-Garcia, Scott K. Reynolds, Troy J. Beukema. 639-642 [doi]
• CMOS Low Noise Amplifier with Capacitive Feedback MatchingEhsan Adabi, Ali M. Niknejad. 643-646 [doi]
• A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB TransmitterVishal V. Kulkarni, Muhammad Muqsith, Hiroki Ishikuro, Tadahiro Kuroda. 647-650 [doi]
• A 3.1-8.0 GHz MB-OFDM UWB transceiver in 0.18μm CMOSHui Zheng, Shuzuo Lou, Dongtian Lu, Cheng Shen, Tatfu Chan, Howard C. Luong. 651-654 [doi]
• A -90 dBm sensitivity 0.13 μm CMOS bluetooth transceiver operating in wide temperature rangeKenichi Agawa, Hideaki Majima, Hiroyuki Kobayashi, Masayuki Koizumi, Shin-ichiro Ishizuka, Takeshi Nagano, Makoto Arai, Yutaka Shimizu, Go Urakawa, Nobuyuki Itoh, Mototsugu Hamada, Nobuaki Otsuka. 655-658 [doi]
• On IIP2 Improvement by Injecting DC Offset at the Mixer in a Wireless ReceiverImtinan Elahi, Khurram Muhammad. 659-662 [doi]
• ECO chip: Energy Consumption Zeroize Chip with a 953MHz High-Sensitivity Radio Wave Detector for Standby Mode ApplicationsToshiyuki Umeda, Shoji Otaka. 663-666 [doi]
• Understanding the Transient Behavior of Injection Locked LC OscillatorsNarasimha Lanka, Satwik A. Patnaik, Ramesh Harjani. 667-670 [doi]
• A Wideband CMOS Linear Digital Phase RotatorHua Wang, Ali Hajimiri. 671-674 [doi]
• Low-Power CMOS Energy Detection Transceiver for UWB Impulse Radio SystemTuan-Anh Phan, Vladimir Krizhanovskii, Sang-Gug Lee. 675-678 [doi]
• An 80 MHz noise optimized continuous-time bandpass filter in 0.25 μm BiCMOSAjay Kumar, Phillip E. Allen. 679-682 [doi]
• A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOSTonse Laxminidhi, Venkata Prasadu, Shanthi Pavan. 683-686 [doi]
• A Q-enhanced Transformer Coupling Dynamic Dual-Mode 5GHz Bandpass NB / Interference Rejection UWB FilterB. Pham, A. Dinh. 687-690 [doi]
• A Process and Temperature Compensated Two-Stage Ring OscillatorKadaba Lakshmikumar, Vinod Mukundagiri, Sander Laurentius Johannes Gierkink. 691-694 [doi]
• Signal Processing Architectures for Low-Noise High-Resolution CMOS Image SensorsShoji Kawahito. 695-702 [doi]
• 2, 11 mA, 23.2 dB-NF, discrete-time filter for GSM/WCDMA/WLAN using retiming techniqueTomohiro Sano, Takaya Maruyama, Ikuo Yasui, Hisayasu Sato, Toshihiko Shimizu. 703-706 [doi]
• An Equalized Ultra-Wideband Channel-Select Filter with a Discrete-Time Charge-Domain Band-Pass IIR FilterAtsushi Yoshizawa, Sachio Iida. 707-710 [doi]
• Cell Broadband Engine Processor Design MethodologyOsamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, Peter Hofstee, C. J. Johnson, Stephen D. Posluszny. 711-716 [doi]
• Implementation of the 65nm Cell Broadband EngineMack W. Riley, Brian K. Flachs, Sang H. Dhong, Gilles Gervais, Steve Weitzel, Michael Wang, David Boerstler, Mark Bolliger, John M. Keaty, Jürgen Pille, R. Berry, Osamu Takahashi, Y. Nishino, T. Uchino. 717-720 [doi]
• Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error DetectionShinichi Yasuda, Shinobu Fujita. 721-724 [doi]
• TM Microprocessor CoreDaniel Murray, James Burnette, Brian Campbell, Mark Chung, Bruce Fernandes, Subhendra Ghosh, Rajat Goel, Greg Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, Fabian Klass, Fang Liu, Anup Mehta, Yamini Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, Sribalan Santhanam, Junji Sugisawa, Shyam Sundar, Honkai John Tam, Ricky Wen, Eric Wu, Jung-Cheng Yeh, John Yong, Sanjay Zambare. 725-728 [doi]
• Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS TechnologyBrian Campbell, James Burnette, Naveen Javarappa, Vincent von Kaenel. 729-732 [doi]
• Process-Tolerant Low-Power Adaptive Pipeline under Scaled-VddSwaroop Ghosh, Pooja Batra, Keejong Kim, Kaushik Roy. 733-736 [doi]
• ASIC Design and Verification in an FPGA EnvironmentDejan Markovic, Chen Chang, Brian C. Richards, Hayden Kwok-Hay So, Borivoje Nikolic, Robert W. Brodersen. 737-740 [doi]
• mm-Wave Silicon ICs: Challenges and OpportunitiesAli Hajimiri. 741-747 [doi]
• 65-nm CMOS, W-Band Receivers for Imaging ApplicationsKeith W. Tang, Mehdi Khanpour, Patrice Garcia, Christophe Gamier, Sorin P. Voinigescu. 749-752 [doi]
• A 4-channel 24-27 GHz UWB phased array transmitter in 0.13 μm CMOS for vehicular radarHarish Krishnaswamy, Hossein Hashemi. 753-756 [doi]
• A CMOS 22-29GHz Receiver Front-End for UWB Automotive Pulse-RadarsVipul Jain, Sriramkumar Sundararaman, Payam Heydari. 757-760 [doi]
• An X- and Ku-Band 8-Element Linear Phased Array ReceiverKwang-Jin Koh, Gabriel M. Rebeiz. 761-764 [doi]
• A 30-40 GHz 1: 16 Internally Matched SiGe Active Power Divider for Phased Array TransmittersJason W. May, Gabriel M. Rebeiz. 765-768 [doi]
• A 60 GHz Power Amplifier in 90nm CMOS TechnologyBabak Heydari, Mounir Bohsali, Ehsan Adabi, Ali M. Niknejad. 769-772 [doi]
• At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted?Antonis Papanikolaou, Miguel Miranda, Pol Marchal, Bart Dierickx, Francky Catthoor. 773-778 [doi]
• Process/Product Interactions in a Concurrent Design EnvironmentLarry Bair. 779-782 [doi]
• Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance EffectYasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye. 783-786 [doi]
• An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAMHyejung Kim, Kyomin Sohn, Jerald Yoo, Hoi-Jun Yoo. 787-790 [doi]
• A 180 Kbit Embeddable MRAM Memory ModuleJoseph J. Nahas, Thomas W. Andre, Chitra Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino. 791-794 [doi]
• A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BISTDarren Anand, Jim Covino, Jeffrey Dreibelbis, John Fifield, Kevin Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale Pontius, Michael Roberge, Stephen Sliva. 795-798 [doi]
• Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic ChipsNorman Robson, John Safran, Chandrasekharan Kothandaraman, Alberto Cestero, Xiang Chen, Raj Rajeevakumar, Alan Leslie, Dan Moy, Toshiaki Kirihata, Subramanian S. Iyer. 799-804 [doi]
• Advanced Design Techniques for Integrated Voltage Controlled LC OscillatorsPeter R. Kinget, Babak Soltanian, Songtao Xu, Shih-An Yu. 805-811 [doi]
• A 0.5-V 16 GHz-20 GHz differential injection-locked divider in 0.18-μm CMOS processHui Zheng, Howard C. Luong. 813-816 [doi]
• A 1V 4 GHz-and-10 GHz transformer-based dual-band quadrature VCO in 0.18 μm CMOSSujiang Rong, Howard C. Luong. 817-820 [doi]
• A CMOS Image Sensor for DNA MicroarraysSamir Parikh, P. Glenn Gulak, Paul Chow. 821-824 [doi]
• Active CMOS Array for Electrochemical Sensing of BiomoleculesPeter M. Levine, Ping Gong, Kenneth L. Shepard, Rastislav Levicky. 825-828 [doi]
• A CMOS Array Sensor for Sub-800-ps Time-Resolved Fluorescence DetectionTa-chien Huang, Sebastian Sorgenfrei, Kenneth L. Shepard, Ping Gong, Rastislav Levicky. 829-832 [doi]
• A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression CircuitsYukinari Nishikawa, Shoji Kawahito, Masanori Furuta, Toshihiro Tamura. 833-836 [doi]
• Integration of CMOS and MEMS Technologies in the Development of a Neural Imaging and Interface Device: Showcase of an Emerging Bioimaging TechniqueDavid C. Ng, Taro Mizuno, Takashi Tokuda, Masahiro Nunoshita, Hideki Tamura, Yasuyuki Ishikawa, Sadao Shiosaka, Jun Ohta. 837-840 [doi]
• Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot SpotsGang Huang, Deepak C. Sekar, Azad Naeemi, Kaveh Shakeri, James D. Meindl. 841-844 [doi]
• Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic CircuitsChristopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram. 845-848 [doi]
• Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for IsolationDaisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata. 849-852 [doi]
• Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon SubstratesBrett Peterson, Kartikeya Mayaram, Terri S. Fiez. 853-856 [doi]
• Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-AWalter Fergusson, Rakesh H. Patel, William Bereza. 857-860 [doi]
• Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF ApplicationsIoannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski. 861-864 [doi]
• Accurate Modeling of RF Circuit Blocks: Weakly-Nonlinear Narrowband LNAsJeroen A. Croon, D. M. W. Leenaerts, Dick B. M. Klaassen. 865-868 [doi]
• Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space ExplorationMasanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng. 869-872 [doi]