Harold Pilo - researchr alias

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Viewing Publication 1 - 10 from 10

2025

2 380/540mV Dual-Rail SRAM in 3nm-FinFET TechnologyHarold Pilo, John Barth 0001, Kapil Dev Dwivedi, Peter Lee, Vikram Kumar, Prasanna Nalawar, Yogeshbhai Patel, Shailendra Sharad, Shakti Singh. isscc 2025: 498-500 [doi]

2013

A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reductionHarold Pilo, Chad A. Adams, Igor Arsovski, Robert M. Houle, Steve Lamphier, Michael M. Lee, Frank Pavlik, Sushma N. Sambatur, Adnan Seferagic, Richard Wu, Mohammad I. Younus. isscc 2013: 322-323 [doi]

2012

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability EnhancementsHarold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic. jssc, 47(1):97-106, 2012. [doi]

2011

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancementsHarold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens. isscc 2011: 254-256 [doi]

2009

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power ManagementVinod Ramadurai, Harold Pilo, John Andersen, Geordie Braceras, John Gabric, Daniel Geise, Steve Lamphier, Yue Tan. jssc, 44(1):155-162, 2009. [doi]

2008

A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power ManagementHarold Pilo, Vaidyanathan Ramadurai, Geordie Braceras, John Gabric, Steve Lamphier, Yue Tan. isscc 2008: 378-379 [doi]

2007

An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating VoltageHarold Pilo, Charlie Barwin, Geordie Braceras, Chris Browning, Steve Lamphier, Fred Towler. jssc, 42(4):813-819, 2007. [doi]

A 550ps Access-Time Compilable SRAM in 65nm CMOS TechnologyLarry Wissel, Harold Pilo, Chris LeBlanc, Xiaopeng Wang, Steve Lamphier, Michael Fragano. cicc 2007: 21-24 [doi]

2003

A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interfaceHarold Pilo, Darren Anand, John Barth 0001, Steve Burns 0001, Phil Corson, Jim Covino, Steve Lamphier. jssc, 38(11):1974-1980, 2003. [doi]

2000

An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pinHarold Pilo, Archie Allen, Jim Covino, Patrick Hansen, Steve Lamphier, Chris Murphy, Terry Traver, Pui Yee. jssc, 35(11):1641-1647, 2000. [doi]

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