Alberto Cestero - researchr alias

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Viewing Publication 1 - 9 from 9

2021

3D-Split SRAM: Enabling Generational Gains in Advanced CMOSR. Mathur, M. Bhargava, H. Perry, Alberto Cestero, F. Frederick, S. Hung, C. Chao, D. Smith, D. Fisher, Norman Robson, X. Xu, Pranavi Chandupatla, R. Balachandran, S. Sinha, B. Cline, Jaydeep P. Kulkarni. cicc 2021: 1-2 [doi]

2018

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process ComplexityBalaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer. jssc, 53(3):949-960, 2018. [doi]

2016

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexityJanakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer. vlsic 2016: 1-2 [doi]

2013

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAMSami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer. jssc, 48(4):940-947, 2013. [doi]

A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAMSami Rosenblatt, Srivatsan Chellappa, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer. jssc, 48(11):2934-2943, 2013. [doi]

2012

Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAMDaniel Fainstein, Sami Rosenblatt, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer. vlsic 2012: 146-147 [doi]

2007

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic ChipsNorman Robson, John Safran, Chandrasekharan Kothandaraman, Alberto Cestero, Xiang Chen, Raj Rajeevakumar, Alan Leslie, Dan Moy, Toshiaki Kirihata, Subramanian S. Iyer. cicc 2007: 799-804 [doi]

2005

An 800-MHz embedded DRAM with a concurrent refresh modeToshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer. jssc, 40(6):1377-1387, 2005. [doi]

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