Abstract is missing.
- A reconfigurable SIMO system with 10-output dual-bus DC-DC converter using the load balancing function in group allocator for diversified load conditionSe-un Shin, Min-Yong Jung, Kiduk Kim, Sang-Hui Park, Yeunhee Huh, Changsik Shin, Se-Hong Park, Jun-Suk Bang, Jong-Beom Baek, Sung-Won Choi, Yong-Min Ju, Gyu-Hyeong Cho. 1-2 [doi]
- Features of retinal prosthesis using suprachoroidal transretinal stimulation from an electrical circuit perspectiveYasuo Terasawa, Kenzo Shodo, Koji Osawa, Jun Ohta. 1-2 [doi]
- 2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOSPhil Knag, Chester Liu, Zhengya Zhang. 1-2 [doi]
- An 8.3M-pixel 480fps global-shutter CMOS image sensor with gain-adaptive column ADCs and 2-on-1 stacked device structureYusuke Oike, Kentaro Akiyama, Luong D. Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito Sakano, Yoshiaki Kitano, Takuya Nakamura, Takayuki Toyama, Hayato Iwamoto, Takayuki Ezaki. 1-2 [doi]
- A fully integrated 144 MHz wireless-power-receiver-on-chip with an adaptive buck-boost regulating rectifier and low-loss H-Tree signal distributionChul Kim, Jiwoong Park, Abraham Akinin, Sohmyung Ha, Rajkumar Kubendran, Hui Wang, Patrick P. Mercier, Gert Cauwenberghs. 1-2 [doi]
- An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting techniqueSho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Dong Ruibing, Shiro Dosho, Noboru Ishihara, Kazuya Masu. 1-2 [doi]
- A 2.4-GHz 6.4-mW fractional-N inductorless RF synthesizerLong Kong, Behzad Razavi. 1-2 [doi]
- 1/2 resolution silicon oscillating accelerometer with build-in Σ-Δ frequency-to-digital converterJian Zhao, Xi Wang, Yang Zhao, Guo Ming Xia, An Ping Qiu, Yan Su, Yong Ping Xu. 1-2 [doi]
- 1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decisionZhewei Jiang, Joao Pedro Cerqueira, Seongjong Kim, Qi Wang, Mingoo Seok. 1-2 [doi]
- A 65nm CMOS transceiver with integrated active cancellation supporting FDD from 1GHz to 1.8GHz at +12.6dBm TX power leakageSameet Ramakrishnan, Lucas Calderin, Antonio Puglielli, Elad Alon, Ali M. Niknejad, Borivoje Nikolic. 1-2 [doi]
- A 28nm CMOS ultra-compact thermal sensor in current-mode techniqueMatthias Eberlein, Idan Yahav. 1-2 [doi]
- 28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applicationsR. Ranica, Nicolas Planes, Vincent Huard, Olivier Weber, D. Noblet, Damien Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars, A. Villaret, M. Parra, Sébastien Haendler, M. Quoirin, Florian Cacho, C. Julien, F. Terrier, Lorenzo Ciampolini, David Turgis, Christophe Lecocq, Franck Arnaud. 1-2 [doi]
- A 180 mW multistandard TV tuner in 28 nm CMOSJianhong Xiao, Weinan Gao, Xiaojing Xu, Dave S.-H. Chang, Jiang Cao, Runhua Sun, Vijay Periasamy, Ning-Yi Wang, Xi Chen, Greg Unruh, Takayuki Hayashi, Tai-Hong Chih, Lakshminarasimhan Krishnan, Kuo-Ken Huang, Sunny Raj Dommaraju, Guowen Wei, Bo Shen, Ardie Venes, Dongsoo Koh, James Y. C. Chang. 1-2 [doi]
- A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFESewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim. 1-2 [doi]
- A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor arrayBrent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas. 1-2 [doi]
- A machine-learning classifier implemented in a standard 6T SRAM arrayJintao Zhang, Zhuo Wang, Naveen Verma. 1-2 [doi]
- An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCsYosuke Ogasawara, Hiroki Sakurai, Ryuichi Fujimoto, Kenichi Sami. 1-2 [doi]
- A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loopYongsun Lee, Heein Yoon, Mina Kim, Jaehyouk Choi. 1-2 [doi]
- Digital PLL for phase noise cancellation in ring oscillator-based I/Q receiversZuow-Zun Chen, Yilei Li, Yen-Cheng Kuan, Boyu Hu, Chien-Heng Wong, Mau-Chung Frank Chang. 1-2 [doi]
- A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integratorYi Zhang, Chia-Hung Chen, Tao He, Gabor C. Temes. 1-2 [doi]
- A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DACSung-En Hsieh, Chih-Cheng Hsieh. 1-2 [doi]
- A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiographyC. Chen, Z. Chen, D. Bera, S. B. Raghunathan, M. Shabanimotlagh, E. Noothout, Z. Y. Chang, J. Ponte, C. Prins, H. J. Vos, J. G. Bosch, M. D. Verweij, N. de Jong, Michiel A. P. Pertijs. 1-2 [doi]
- A 50MHz 5V 3W 90% efficiency 3-level buck converter with real-time calibration and wide output range for fast-DVS in 65nm CMOSXun Liu, Cheng Huang, Philip K. T. Mok. 1-2 [doi]
- SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shapeGuerric de Streel, François Stas, Thibaut Gurne, François Durant, Charlotte Frenkel, David Bol. 1-2 [doi]
- A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOSA. K. M. Delwar Hossain, Aurangozeb, Maruf Mohammad, Masum Hossain. 1-2 [doi]
- Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodesS. C. Song, J. Xu, D. Yang, K. Rim, P. Feng, J. Bao, J. Zhu, J. Wang, G. Nallapati, M. Badaroglu, P. Narayanasetti, B. Bucki, J. Fischer, Geoffrey Yeap. 1-2 [doi]
- A 0.3-2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNetsBert Moons, Marian Verhelst. 1-2 [doi]
- 250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOSSudhir Satpathy, Sanu Mathew, Vikram Suresh, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory Chen, Ram Krishnamurthy. 1-2 [doi]
- Accelerating the Sensing world through imaging evolutionTetsuo Nomoto, Yusuke Oike, Hayato Wakabayashi. 1-4 [doi]
- A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoTRichard Dorrance, Dejan Markovic. 1-2 [doi]
- A transformer-based digital isolator with 20kVPK surge capability and > 200kV/µS Common Mode Transient ImmunityRuida Yun, James Sun, Eric Gaalaas, Baoxing Chen. 1-2 [doi]
- A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOSBenwei Xu, Yuan Zhou, Yun Chiu. 1-2 [doi]
- Multi-modal smart bio-sensing SoC platform with >80dB SNR 35µA PPG RX chainAjit Sharma, Seung-Bae Lee, Arup Polley, Sriram Narayanan, Wen Li, Terry Sculley, Srinath Ramaswamy. 1-2 [doi]
- A 2.4GHz ternary sequence spread spectrum OOK transceiver with harmonic spur suppression and dual-mode detection architecture for ULP wearable devicesSeong Joong Kim, Chang Soon Park, Youngkyu Kim, Seok-Ju Yun, Young-Jun Hong, Sang-Gug Lee. 1-2 [doi]
- A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technologyTakashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Kenichi Akita, Hideo Arimoto, Masaru Kokubo, Tatemi Ido. 1-2 [doi]
- Lensless Smart Sensors: Optical and thermal sensing for the Internet of ThingsPatrick Gill, Thomas Vogelsang. 1-2 [doi]
- 2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOSChao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ximenes, Robert Bogdan Staszewski. 1-2 [doi]
- An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADCMinseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Chulwoo Kim, Dennis Sylvester, David Blaauw, Wanyeong Jung. 1-2 [doi]
- A 260µW infrared gesture recognition system-on-chip for smart devicesSechang Oh, Ngoc Le Ba, Suyoung Bang, Junwon Jeong, David Blaauw, Tony T. Kim, Dennis Sylvester. 1-2 [doi]
- A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedbackAnkesh Jain, Shanthi Pavan. 1-2 [doi]
- An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering techniqueAlvin Li, Yue Chao, Xuan Chen, Liang Wu, Howard Luong. 1-2 [doi]
- 2 time-domain impedance sensor that provides values of resistance and capacitanceYan Hong, Yong Wang, Wang Ling Goh, Yuan Gao, Lei Yao. 1-2 [doi]
- A high-density CMOS multi-modality joint sensor/stimulator array with 1024 pixels for holistic real-time cellular characterizationJong Seok Park, Taiyun Chi, Amy Su, Chengjie Zhu, Jung Hoon Sung, Hee Cheol Cho, Mark P. Styczynski, Hua Wang. 1-2 [doi]
- A 380pW dual mode optical wake-up receiver with ambient noise cancellationWootaek Lim, Tae-Kwang Jang, Inhee Lee, Hun-Seok Kim, Dennis Sylvester, David Blaauw. 1-2 [doi]
- A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOSHiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka. 1-2 [doi]
- A fully integrated GaN-based power IC including gate drivers for high-efficiency DC-DC ConvertersShinji Ujita, Yusuke Kinoshita, Hidekazu Umeda, Tatsuo Morita, Kazuhiro Kaibara, Satoshi Tamura, Masahiro Ishida, Tetsuzo Ueda. 1-2 [doi]
- 2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access timeMakoto Yabuuchi, Yohei Sawada, Toshiaki Sano, Yuichiro Ishii, Shinji Tanaka, Miki Tanaka, Koji Nii. 1-2 [doi]
- A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyondY. Tsuji, X. Bai, Ayuka Morioka, Makoto Miyamura, Ryusuke Nebashi, T. Sakamoto, Munehiro Tada, Naoki Banno, K. Okamoto, N. Iguchi, H. Hada, Tadahiko Sugibayashi. 1-2 [doi]
- 2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOSAmit Agarwal, Steven Hsu, Mark Anders, Sanu Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir Satpathy, Ram Krishnamurthy. 1-2 [doi]
- 3.5mW 1MHz AM detector and digitally-controlled tuner in a-IGZO TFT for wireless communications in a fully integrated flexible system for audio bagTilo Meister, K. Ishida, Corrado Carta, R. Shabanpour, B. Kherdmand Boroujeni, Niko Munzenrieder, Luisa Petti, Giovanni A. Salvatore, G. Schmidt, Pol Ghesquière, Stefan Kiefl, G. De Toma, T. Faetti, Arved C. Hübler, Gerhard Tröster, Frank Ellinger. 1-2 [doi]
- A microcontroller with 96% power-conversion efficiency using stacked voltage domainsKristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud van der Wel, Hamed Fatemi, José Pineda de Gyvez, Kofi Makinwa. 1-2 [doi]
- A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOSSanu Mathew, Sudhir Satpathy, Vikram Suresh, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Greg Chen, Ram Krishnamurthy, Vivek De. 1-2 [doi]
- Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution coreMinki Cho, Carlos Tokunaga, Stephen T. Kim, James Tschanz, Muhammad M. Khellah, Vivek De. 1-2 [doi]
- A 16-channel noise-shaping machine learning analog-digital interfaceFred N. Buhler, Adam E. Mendrela, Yong Lim, Jeffrey A. Fredenburg, Michael P. Flynn. 1-2 [doi]
- ForewordJeffrey C. Gealow, Masato Motomura. 1-2 [doi]
- A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applicationsYen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, Wei-Min Chan, Jhon-Jhy Liaw, Hung-Jen Liao, Jonathan Chang. 1-2 [doi]
- A 220pJ/pixel/frame CMOS image sensor with partial settling readout architectureSuyao Ji, Jing Pu, ByongChan Lim, Mark Horowitz. 1-2 [doi]
- An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOSSomnath Paul, Vinayak Honkote, Ryan Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Sandeep Jain, Sriram R. Vangal, James Tschanz, Vivek De. 1-2 [doi]
- 2 5.2 mW/tap 20 GBd inductor-less 5-tap analog RX-FFERyan Boesch, Kevin Zheng, Boris Murmann. 1-2 [doi]
- A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitterFeng-Wei Kuo, Sandro Binsfeld Ferreira, Masoud Babaie, Ron Chen, Lan-chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Guanzhong Huang, Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski. 1-2 [doi]
- A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHzVishnu Ravinuthula, William Bright, Mark Weaver, Kenneth Maclean, Scott Kaylor, Sidharth Balasubramanian, Jesse Coulon, Robert Keller, Bao Nguyen, Ebenezer Dwobeng. 1-2 [doi]
- A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding schemeIl-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Young Jae Jang, Young-Chul Cho, Young-Soo Sohn, Jung Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong June Park. 1-2 [doi]
- A microelectrode array with 8, 640 electrodes enabling simultaneous full-frame readout at 6.5 kfps and 112-channel switch-matrix readout at 20 kS/sX. Yuan, S. Kim, J. Juyon, M. D'Urbino, T. Bullmann, Y. Chen, Alexander Stettler, Andreas Hierlemann, Urs Frey. 1-2 [doi]
- A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibrationArindam Sanyal, Nan Sun. 1-2 [doi]
- Motor Control used to be boringAlexander Tessarolo. 1-2 [doi]
- 95% light-load efficiency single-inductor dual-output DC-DC buck converter with synthesized waveform control technique for USB type-CWen-Hau Yang, Chiun-He Lin, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai, Jui-Lung Chen. 1-2 [doi]
- Innovative system on chip platform for Smart Grids and internet of energy applicationsAlessandro Moscatelli. 1-2 [doi]
- A 35fJ/Step differential successive approximation capacitive sensor readout circuit with quasi-dynamic operationHesham Omran, Abdulaziz Alhoshany, Hamzah Alahmadi, Khaled N. Salama. 1-2 [doi]
- A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nmYiqun Zhang 0002, Kaiyuan Yang, Mehdi Saligane, David Blaauw, Dennis Sylvester. 1-2 [doi]
- A 7-to-18.3GHz compact transformer based VCO in 16nm FinFETMayank Raj, Parag Upadhyaya, Yohan Frans, Ken Chang. 1-2 [doi]
- A 14.6mW 12b 800MS/s 4×time-interleaved pipelined SAR ADC achieving 60.8dB SNDR with Nyquist input and sampling timing skew of 60fsrms without calibrationYuan-Ching Lien. 1-2 [doi]
- A 58.6mW real-time programmable object detector with multi-scale multi-object support using deformable parts model on 1920×1080 video at 30fpsAmr Suleiman, Zhengdong Zhang, Vivienne Sze. 1-2 [doi]
- A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and ditherAhmed M. A. Ali, Huseyin Dinc, Paritosh Bhoraskar, Scott Puckett, Andy Morgan, Ning Zhu, Qicheng Yu, Christopher Dillon, Bryce Gray, Jonathan Lanford, Matthew McShea, Ushma Mehta, Scott Bardsley, Peter R. Derounian, Ryan Bunch, Ralph Moore, Gerry Taylor. 1-2 [doi]
- A 66pW discontinuous switch-capacitor energy harvester for self-sustaining sensor applicationsXiao Wu, Yao Shi, Supreet Jeloka, Kaiyuan Yang, Inhee Lee, Dennis Sylvester, David Blaauw. 1-2 [doi]
- A field-programmable mixed-signal IC with time-domain configurable analog blocksYunju Choi, Yoontaek Lee, Seung-Heon Baek, Sung-Joon Lee, Jaeha Kim. 1-2 [doi]
- 2 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detectorWei Tang, Chia-Hsiang Chen, Zhengya Zhang. 1-2 [doi]
- A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOSBharath Raghavan, Aida Varzaghani, Lakshmi P. Rao, Henry Park, Xiaochen Yang, Zhi Huang, Yu Chen, Rama Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, Afshin Momtaz, Namik Kocaman. 1-2 [doi]
- A ± 36A integrated current-sensing system with 0.3% gain error and 400µA offset from -55°C to +85°CSaleh Heidary Shalmany, Dieter Draxelmayr, Kofi A. A. Makinwa. 1-2 [doi]
- Enabling future progress in machine-learningOlivier Temam. 1-3 [doi]
- Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centersAtsuro Kobayashi, Tsukasa Tokutomi, Ken Takeuchi. 1-2 [doi]
- A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOIMilovan Blagojevic, Martin Cochet, Ben Keller, Philippe Flatresse, Andrei Vladimirescu, Borivoje Nikolic. 1-2 [doi]
- A BJT-based temperature-to-digital converter with ±60mK (3σ) inaccuracy from -70°C to 125°C in 160nm CMOSBahman Yousefzadeh, Saleh Heidary Shalmany, Kofi Makinwa. 1-2 [doi]
- A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOSYuan Du, Wei-Han Cho, Yilei Li, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, Sheau Jiung Lee, Mau-Chung Frank Chang. 1-2 [doi]
- A wireless power transfer system with enhanced response and efficiency by fully-integrated fast-tracking wireless constant-idle-time control for implantsCheng Huang, Toru Kawajiri, Hiroki Ishikuro. 1-2 [doi]
- A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOSJae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen. 1-2 [doi]
- A 450mV timing-margin-free waveform sorter based on body swapping error correctionSeongjong Kim, Joao Pedro Cerqueira, Mingoo Seok. 1-2 [doi]
- A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systemsQing Dong, Kaiyuan Yang, David Blaauw, Dennis Sylvester. 1-2 [doi]
- 80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexityJanakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer. 1-2 [doi]
- A 2.048 Mb/s full-duplex free-space optical transceiver IC for a real-time in vivo neurofeedback mouse experiment under social interactionGunpil Hwang, JongKwan Choi, Jaehyeok Yang, Sungmin Lim, Jae-Myoung Kim, MinGyu Choi, Dae-Shik Kim, Kiuk Gwak, Jinwoo Jeon, Hee-Sup Shin, Il-Hwan Choi, Sol Park, Hyeon-Min Bae. 1-2 [doi]
- An FPGA-accelerated partial image matching engine for massive media data searching systemsTakashi Shimizu, Yasumoto Tomita, Hidetoshi Matsumura, Masahiko Sugimura, Hironobu Yamasaki, David Thach, Takashi Miyoshi, Takayuki Baba, Yasuhiro Watanabe, Atsushi Ike. 1-2 [doi]
- th-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOSYang Xu, Spencer Leuenberger, Praveen Kumar Venkatachala, Un-Ku Moon. 1-2 [doi]
- A dead-time free global shutter CMOS image sensor with in-pixel LOFIC and ADC using pixel-wis e connectionsHidetake Sugo, Shunichi Wakashima, Rihito Kuroda, Yuichiro Yamashita, Hirofumi Sumi, Tzu-Jui Wang, Po-Sheng Chou, Ming-Chieh Hsu, Shigetoshi Sugawa. 1-2 [doi]
- A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technologyParag Upadhyaya, Ade Bekele, Didem Turkur Melek, Haibing Zhao, Jay Im, Junho Cho, Kee Hian Tan, Scott McLeod, Stanley Chen, Wenfeng Zhang, Yohan Frans, Ken Chang. 1-2 [doi]
- 2 per channel in 65-nm CMOSSeyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim. 1-2 [doi]
- A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effectKoji Obata, Kazuo Matsukawa, Takuji Miki, Yusuke Tsukamoto, Koji Sushihara. 1-2 [doi]
- -197dBc/Hz FOM 4.3-GHz VCO Using an addressable array of minimum-sized nmos cross-coupled transistor pairs in 65-nm CMOSA. Jha, A. Ahmadi, S. Kshattry, T. Cao, K. Liao, G. Yeap, Y. Makris, K. K. O. 1-2 [doi]
- A wearable ear-EEG recording system based on dry-contact active electrodesXiong Zhou, Qiang Li, Soren Kilsgaard, Farshad Moradi, Simon Lind Kappel, Preben Kidmose. 1-2 [doi]
- A chopping switched-capacitor RF receiver with integrated blocker detection, +31dBm OB-IIP3, and +15dBm OB-B1dBYang Xu, Peter R. Kinget. 1-2 [doi]
- A 10Gb/s, 342fJ/bit micro-ring modulator transmitter with switched-capacitor pre-emphasis and monolithic temperature sensor in 65nm CMOSSaman Saeedi, Azita Emami. 1-2 [doi]
- A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFETYohan Frans, Mohamed Elzeftawi, Hiva Hedayati, Jay Im, Vassili Kireev, Toan Pham, Jaewook Shin, Parag Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang. 1-2 [doi]
- 2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gatingZ. Chen, S. H. Kulkarni, V. E. Dorgan, U. Bhattacharya, K. Zhang. 1-2 [doi]
- Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifierSangheon Lee, Jeonghwan Song, Changhyuk Seong, Jiyong Woo, Jong Moon Choi, Soon-Chan Kwon, Ho Joon Kim, Hyun-Suk Kang, Soo Gil Kim, Hoe Gwon Jung, Kee-Won Kwon, Hyunsang Hwang. 1-2 [doi]
- A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOSYing-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu. 1-2 [doi]
- 2 6T bitcell in a 16nm FinFET CMOS processAzeez Bhavnagarwala, Imran Iqbal, An Nguyen, David Ondricek, Vikas Chandra, Robert C. Aitken. 1-2 [doi]
- Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOSTatsuya Onuki, Wataru Uesugi, Hikaru Tamura, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, T. R. Yew, Chen Bin Lin, J.-Y. Wu, Chi-Chang Shuai, Shao Hui Wu, James Myers, Klaus Doppler, Masahiro Fujita, Shunpei Yamazaki. 1-2 [doi]
- 2 implantable seizure control SoC with sub-μW/channel consumption and closed-loop stimulation in 0.18µm CMOSMahsa Shoaran, Masoud Shahshahani, Masoud Farivar, Joyel Almajano, Amirhossein Shahshahani, Alexandre Schmid, Anatol Bragin, Yusuf Leblebici, Azita Emami. 1-2 [doi]