Toshihiko Mori - researchr alias

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Viewing Publication 1 - 25 from 25

2022

Highly power-efficient (2 pJ/bit), 128Gbps 16QAM signal generation of coherent optical DAC transmitter using 28-nm CMOS driver and all-silicon segmented modulatorYohei Sobu, Guoxiu Huang, Toshihiko Mori, Yukito Tsunoda, Takuji Yamamoto, Shinsuke Tanaka, Takeshi Hoshida. ofc 2022: 1-3 [doi]

2019

Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product designYukito Tsunoda, Takahiro Notsu, Yasufumi Sakai, Naoki Hamada, Toshihiko Mori, Teruo Ishihara, Atsuki Inoue. gecco 2019: 405-406 [doi]

2018

Error-Free Loopback of a Compact 25 Gb/s × 4 ch WDM Transceiver Assembly Incorporating Silicon (De)Multiplexers with Automated Phase-Error CorrectionTomoyuki Akiyama, Tsuyoshi Aoki, Takasi Simoyama, Akio Sugama, Shigeaki Sekiguchi, Yohei Sobu, Shinsuke Tanaka, Yu Tanaka, Seok-Hwan Jeong, Motoyuki Nishizawa, Nobuaki Hatori, Akinori Hayakawa, Toshihiko Mori. ofc 2018: 1-3 [doi]

2017

2016

24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDRYukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Jun Matsui, Takashi Shiraishi, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura. ofc 2016: 1-3 [doi]

2015

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOSTakayuki Shibasaki, Yukito Tsunoda, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura. isscc 2015: 1-3 [doi]

25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICsYukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura. ofc 2015: 1-3 [doi]

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOSYukito Tsunoda, Takayuki Shibasaki, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura. isscc 2015: 1-3 [doi]

2014

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTEKazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Seitaro Kawai, Shinji Yamaura, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori. isscc 2014: 60-61 [doi]

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTEKazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Shigeaki Kawai, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori. jssc, 49(12):2915-2924, 2014. [doi]

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOSTakayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura. vlsic 2014: 1-2 [doi]

2012

2010

2007

A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage BiasingMasato Yoshioka, Masahiro Kudo, Toshihiko Mori, Sanroku Tsukamoto. isscc 2007: 452-614 [doi]

2003

A CMOS multichannel 10-Gb/s transceiverHideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura. jssc, 38(12):2094-2100, 2003. [doi]

1999

Customization Rule Generation for Electronic Sales Promotion System in Wholesale IndustryMasaki Yumoto, Kyungsuk Oh, Norihisa Komoda, Toshihiko Mori. wecwis 1999: 50-55 [doi]

1998

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