Shoichiro Kawashima - researchr alias

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Viewing Publication 1 - 8 from 8

2015

An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar TechnologyShoichiro Kawashima, Keizo Morita, Mitsuharu Nakazawa, Kazuaki Yamane, Mitsuhiro Ogai, Kuninori Kawabata, Kazuaki Takai, Yasuhiro Fujii, Ryoji Yasuda, Wensheng Wang, Yukinobu Hikosaka, Ken'ichi Inoue. ieicet, 98-C(11):1047-1057, 2015. [doi]

2007

A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application ChipShoichiro Kawashima, Isao Fukushi, Keizo Morita, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Kazuaki Yamane, Tomohisa Hirayama, Toru Endo. ieicet, 90-C(10):1941-1948, 2007. [doi]

2004

Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM)Yadollah Eslami, Ali Sheikholeslami, Shoichi Masui, Toru Endo, Shoichiro Kawashima. jssc, 39(11):2024-2031, 2004. [doi]

2003

A ferroelectric memory-based secure dynamically programmable gate arrayShoichi Masui, Tsuzumi Ninomiya, Michiya Oura, Wataru Yokozeki, Kenji Mukaida, Shoichiro Kawashima. jssc, 38(5):715-725, 2003. [doi]

A current-based reference-generation scheme for 1T-1C ferroelectric random-access memoriesJoseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima. jssc, 38(3):541-549, 2003. [doi]

2002

Bitline GND sensing technique for low-voltage operation FeRAMShoichiro Kawashima, Toru Endo, Akira Yamamoto, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Keizo Morita, Masaki Aoki. jssc, 37(5):592-598, 2002. [doi]

A 16 kb 1T1C FeRAM test chip using current-based reference schemeJoseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima. cicc 2002: 107-110 [doi]

1998

A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM'sShoichiro Kawashima, Toshihiko Mori, Ryuhei Sasagawa, Makoto Hamaminato, Shigetoshi Wakayama, Kazuo Sukegawa, Isao Fukushi. jssc, 33(5):793-799, 1998. [doi]

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