Amir Amirkhany - researchr alias

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Viewing Publication 1 - 27 from 27

2022

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS ProcessTianyu Wang 0006, Da Wei, Ranick Ng, Gaurav Malhotra, Anup P. Jose, Amir Amirkhany, Pavan Kumar Hanumolu. jssc, 57(8):2521-2531, 2022. [doi]

Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)Amir Amirkhany, Tanay Karnik, Shidhartha Das, Jun Deguchi, Yasuhiko Taito. jssc, 57(1):3-5, 2022. [doi]

2021

Session 11 Overview: Advanced Wireline Links and Techniques Wireline SubcommitteeMike Shuo-Wei Chen, Wei-Zen Chen, Amir Amirkhany. isscc 2021: 178-179 [doi]

Baud rate pattern-adaptable dual loop clock recovery for high speed serial linksGaurav Malhotra, Jalil Kamali, Amir Amirkhany. acssc 2021: 43-48 [doi]

2019

A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS ProcessAnup Jose, Valentin Abramzon, Mohamed Elzeftawi, Michael Wang, Kyunglok Kim, Younghoon Song, Shiva Moballegh, Jalil Kamali, Amir Amirkhany. cicc 2019: 1-4 [doi]

2016

23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displaysMohammad Hekmat, Sanquan Song, Nancy Jaffari, Sabarish Sankaranarayanan, Chaofeng Huang, Minghui Han, Gaurav Malhotra, Jalil Kamali, Amir Amirkhany, Wei Xiong. isscc 2016: 402-403 [doi]

2013

2012

A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical linkAmir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan. isscc 2012: 138-140 [doi]

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical LinkAmir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan. jssc, 47(12):3208-3219, 2012. [doi]

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibrationKambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Murugan, Wendemagegnehu T. Beyene, Ken Chang, Chuck Yuan. isscc 2012: 132-134 [doi]

2011

2010

A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed LinksMahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani. jssc, 45(8):1533-1541, 2010. [doi]

A Low-Cost Resonance Mitigation Technique for Multidrop Memory InterfacesFarshid Aryanfar, Amir Amirkhany. tcas, 57-II(5):339-342, 2010. [doi]

2009

A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed linksMahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani. cicc 2009: 125-128 [doi]

2008

A 24 Gb/s Software Programmable Analog Multi-Tone TransmitterAmir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi Kollipara, Vladimir Stojanovic, Mark Horowitz. jssc, 43(4):999-1009, 2008. [doi]

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane CommunicationsJafar Savoj, Aliazam Abbasfar, Amir Amirkhany, Metha Jeeradit, Bruno W. Garlepp. jssc, 43(5):1207-1216, 2008. [doi]

2007

2006

Analog Multi-Tone Signaling for High-Speed Backplane Electrical LinksAmir Amirkhany, Ali-Azam Abbasfar, Vladimir Stojanovic, Mark A. Horowitz. globecom 2006: [doi]

2004

Multi-tone signaling for high-speed backplane electrical linksAmir Amirkhany, Vladimir Stojanovic, Mark A. Horowitz. globecom 2004: 1111-1117 [doi]

Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communicationVladimir Stojanovic, Amir Amirkhany, Mark A. Horowitz. icc 2004: 2799-2806 [doi]

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