Anup P. Jose - researchr alias

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Viewing Publication 1 - 7 from 7

2023

A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery LoopMohamed Badr Younis, Mostafa Gamal Ahmed, Tianyu Wang 0006, Ahmed E. AbdelRahman, Mahmoud A. Khalil, Anup P. Jose, Pavan Kumar Hanumolu. vlsit 2023: 1-2 [doi]

2022

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS ProcessTianyu Wang 0006, Da Wei, Ranick Ng, Gaurav Malhotra, Anup P. Jose, Amir Amirkhany, Pavan Kumar Hanumolu. jssc, 57(8):2521-2531, 2022. [doi]

2015

A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOSYohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang. jssc, 50(8):1932-1944, 2015. [doi]

2007

Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip CommunicationAnup P. Jose, Kenneth L. Shepard. jssc, 42(6):1415-1424, 2007. [doi]

2006

Pulsed current-mode signaling for nearly speed-of-light intrachip communicationAnup P. Jose, George Patounakis, Kenneth L. Shepard. jssc, 41(4):772-780, 2006. [doi]

2005

An on-chip jitter measurement circuit with sub-picosecond resolutionKeith A. Jenkins, Anup P. Jose, David F. Heidel. esscirc 2005: 157-160 [doi]

On-Chip Spectrum Analyzer for Analog Built-In Self TestAnup P. Jose, Keith A. Jenkins, Scott K. Reynolds. vts 2005: 131-136 [doi]

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