Jafar Savoj - researchr alias

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Viewing Publication 1 - 23 from 23

2015

2014

2013

2012

2011

Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits ConferenceJafar Savoj, Yiannos Manoli, Hooman Darabi, Yorgos Palaskas, Michael Moyal. jssc, 46(12):2739-2744, 2011. [doi]

High-speed transceivers: Standards, challenges, and futureAli Sheikholeslami, Franz Dielacher, Miki Moyal, Jafar Savoj, John Stonick, Takuji Yamamoto. isscc 2011: 522-523 [doi]

2008

A 24 Gb/s Software Programmable Analog Multi-Tone TransmitterAmir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi Kollipara, Vladimir Stojanovic, Mark Horowitz. jssc, 43(4):999-1009, 2008. [doi]

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane CommunicationsJafar Savoj, Aliazam Abbasfar, Amir Amirkhany, Metha Jeeradit, Bruno W. Garlepp. jssc, 43(5):1207-1216, 2008. [doi]

2007

Time-Variant Characterization and Compensation of Wideband CircuitsAmir Amirkhany, Ali-Azam Abbasfar, Jafar Savoj, Mark A. Horowitz. cicc 2007: 487-490 [doi]

A new technique for characterization of digital-to-analog converters in high-speed systemsJafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz. date 2007: 433-438 [doi]

2005

2003

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detectorJafar Savoj, Behzad Razavi. jssc, 38(1):13-21, 2003. [doi]

2001

Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication SystemsJafar Savoj, Behzad Razavi. dac 2001: 121-126 [doi]

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detectorJafar Savoj, Behzad Razavi. jssc, 36(5):761-768, 2001. [doi]

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