Table of Contents

• A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOSEhsan Zhian Tabasy, Ayman Shafik, S. Huang, N. Yang, Sebastian Hoyos, Samuel Palermo. 1-4 [doi]
• A non-iterative physical procedure for RF CMOS compact model extraction using BSIM6Sriramkumar Venugopalan, Krishnanshu Dandu, Samuel Martin, Richard Taylor, Claude Cirba, Xin Zhang, Ali M. Niknejad, Chenming Hu. 1-4 [doi]
• A CMOS switched-capacitor fractional bandgap referenceWilliam Biederman, Daniel J. Yeager, Elad Alon, Jan M. Rabaey. 1-4 [doi]
• Modeling & design for variability and reliabilityTrent McConaghy, Hidetoshi Onodera. 1-2 [doi]
• 2 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5b/step redundancy and digital metastability correctionR. Vitek, E. Gordon, S. Maerkovich, A. Beidas. 1-4 [doi]
• An integrated MESFET voltage follower LDO for high power and PSR RF and analog applicationsWilliam Lepkowski, Seth J. Wilk, M. Reza Ghajar, Bertan Bakkaloglu, Trevor J. Thornton. 1-4 [doi]
• Online Reinforcement Learning NoC for portable HD object recognition processorJunyoung Park, Injoon Hong, Gyeonghoon Kim, Jinwook Oh, Seungjin Lee, Hoi-Jun Yoo. 1-4 [doi]
• Electronic design automation (EDA) solutions for ESD-robust design and verificationMichael G. Khazhinsky, Shuqing Cao, Harald Gossner, Gianluca Boselli, Melanie Etherton. 1-8 [doi]
• A 7b 1.4GS/s ADC with offset drift suppression techniques for one-time calibrationYuji Nakajima, Norihito Kato, Akemi Sakaguchi, Toshio Ohkido, Kenji Shimomaki, Hiroko Masuda, Chikahiro Shiroma, Michio Yotsuyanagi, Takahiro Miki. 1-4 [doi]
• A 5-300MHz CMOS transceiver for multi-nuclear NMR spectroscopyJaehyup Kim, Bruce Hammer, Ramesh Harjani. 1-4 [doi]
• A 4-bit 12GS/s data acquisition System-on-Chip including a flash ADC and 4-channel DeMUX in 130nm CMOSBehrooz Javid, Payam Heydari. 1-4 [doi]
• Design of organic complementary circuits for RFID tags applicationMathieu Guerin, Emmanuel Bergeret, Evangeline Benevent, Philippe Pannier, Anis Daami, Stéphanie Jacob, Isabelle Chartier, Romain Coppard. 1-4 [doi]
• Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systemsSuyoung Bang, David Blaauw, Dennis Sylvester, Massimo Alioto. 1-4 [doi]
• Design of a monolithic CMOS image sensor integrated focal plane wire-grid polarizer filter mosaicXiaotie Wu, Milin Zhang, Nader Engheta, Jan Van der Spiegel. 1-4 [doi]
• A 57.5-to-90.1GHz magnetically-tuned multi-mode CMOS VCOJun Yin, Howard C. Luong. 1-4 [doi]
• Multi-band, multi-mode, low-power CMOS receiver front-end for sub-GHz ISM/SRD band with narrow channel spacingChiang-Hua Yeh, Han-Chi Hsieh, Peng Xu, Sudipto Chakraborty. 1-4 [doi]
• A 0.6V 2.2mW 58-to-73GHz divide-by-4 injection-locked frequency dividerLiang Wu, Howard C. Luong. 1-4 [doi]
• Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensorsN. C.-J. Chang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis. 1-4 [doi]
• 2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integrationYasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu. 1-4 [doi]
• Large-scale statistical performance modeling of analog and mixed-signal circuitsXin Li, Wangyang Zhang, Fa Wang. 1-8 [doi]
• A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOSKambiz Kaviani, Masum Hossain, Meisam Honarvar Nazari, Fred Heaton, Jihong Ren, Jared Zerbe. 1-4 [doi]
• A Full-Band processor for reduction of RF mixer LO harmonic imagesRay Gomez, Hanli Zou, Binning Chen, Bruce Currivan, Dave (Sung-Hsien) Chang. 1-4 [doi]
• A quantization noise cancelling fractional-N type ΔΣ frequency synthesizer using SAR-based DAC gain calibrationSeungjin Kim, In-Young Lee, Joo-Myoung Kim, Sang-Gug Lee. 1-4 [doi]
• A 100 MHz two-phase four-segment DC-DC converter with light load efficiency enhancement in 0.18 μm CMOS technologyHan Peng, David I. Anderson, Mona Mostafa Hella. 1-4 [doi]
• An 8.5-11.5Gbps SONET transceiver with referenceless frequency acquisitionNamik Kocaman, Siavash Fallahi, Mahyar Kargar, Mehdi Khanpour, Afshin Momtaz. 1-4 [doi]
• o C, 100kHz On-Chip clock source for ultra low power SoCsAatmesh Shrivastava, Benton H. Calhoun. 1-4 [doi]
• Behavioral modeling for RF and AMSColin McAndrew, Brian Chen. 1 [doi]
• Clock-gated harmonic rejection mixersAslam A. Rafi, T. R. Viswanathan. 1-8 [doi]
• EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOSMassimo Alioto, Elio Consoli, Jan M. Rabaey. 1-4 [doi]
• Impact of subthreshold hump on bulk-bias dependence of offset voltage variability in weak and moderate inversion regionsKiyohiko Sakakibara, Toshio Kumamoto, K. Arimoto. 1-4 [doi]
• A supply-voltage scalable, 45 nm CMOS ultra-wideband receiver for mm-wave ranging and communicationSandipan Kundu, Ahmad Khairi, Jeyanandh Paramesh. 1-4 [doi]
• A single-chip x-band chirp radar MMIC with stretch processingJianjun Yu, Feng Zhao, Joseph Cali, Desheng Ma, Xueyang Geng, Fa Foster Dai, J. David Irwin, Andre Aklian. 1-4 [doi]
• Modeling local variation of low-frequency noise in MOSFETs via sum of lognormal random variablesBo Yu, Xin Li, James Yonemura, Zhiyuan Wu, Jung-Suk Goo, Ciby Thuruthiyil, Ali Icel. 1-4 [doi]
• A 0.65V embedded SDRAM with smart boosting and power management in a 45nm CMOS technologySuk-Soo Pyo, Jun Sung Kim, Jung-Han Kim, Hyun-Taek Jung, Tae-Joong Song, Cheol-Ha Lee, Gyun-Hong Kim, Young Keun Lee, Kee Sup Kim. 1-4 [doi]
• Silicon-based THz circuits, systems and applications (Forum)Alberto Valdes-Garcia. 1 [doi]
• Non-load-balance-dependent high efficiency single-inductor multiple-output (SIMO) DC-DC convertersY. H. Ko, Y. S. Jang, S. K. Han, S. G. Lee. 1-4 [doi]
• A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technologyKazuki Fukuoka, R. Mori, A. Kato, Motoshige Igarashi, K. Shibutani, T. Yamaki, Shinji Tanaka, Koji Nii, S. Morita, Takao Koike, Noriaki Sakamoto. 1-4 [doi]
• A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalizationJiangfeng Wu, Chun-Ying Chen, Tianwei Li, Wenbo Liu, Lin He, Shauhyuarn Sean Tsai, Binning Chen, Chun-Sheng Huang, Juo-Jung Hung, Wei-Ta Shih, Hing T. Hung, Steven Jaffe, Loke Tan, Hung Vu. 1-4 [doi]
• Field programmable SONOS ESD protection designJ. Liu, Z. T. Shi, X. Wang, H. Zhao, L. Wang, C. Zhang, Z. Dong, L. Lin, A. Wang, Y. Cheng, B. Zhao. 1-4 [doi]
• A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DACTimir Nandi, Karthikeya Boominathan, Shanthi Pavan. 1-4 [doi]
• Fully integrated capacitive converter with all digital ripple mitigationSudhir S. Kudva, Ramesh Harjani. 1-4 [doi]
• A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double samplingHyunsoo Ha, Yunjae Suh, Seon-Kyoo Lee, Hong June Park, Jae-Yoon Sim. 1-4 [doi]
• A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceiversAtsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda. 1-4 [doi]
• High power, high efficiency stacked mmWave Class-E-like power amplifiers in 45nm SOI CMOSAnandaroop Chakrabarti, Harish Krishnaswamy. 1-4 [doi]
• Flexible solar-energy harvesting system on plastic with thin-film LC oscillators operating above ft for inductively-coupled power deliveryYingzhe Hu, Warren Rieutort-Louis, Liechao Huang, Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma. 1-4 [doi]
• 2 fully on-chip controller with self-error-correction for boost DC-DC converter based on Zero-Order ControlTae-Hwang Kong, Sung-Wan Hong, Sungwoo Lee, Jong-Pil Im, Gyu-Hyeong Cho. 1-4 [doi]
• Modeling the response of Bang-Bang digital PLLs to phase error perturbationsMoataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor. 1-4 [doi]
• A low-phase-noise wide-tuning-range quadrature oscillator in 65nm CMOSGuansheng Li, Ehsan Afshari. 1-4 [doi]
• Compact and behavioral modeling of transistors from NVNA measurements: New flows and future trendsDavid E. Root, Jianjun Xu, Franz Sischka, Mihai Marcu, Jason Horn, R. M. Biernacki, Masaya Iwamoto. 1-6 [doi]
• A current reference pre-charged zero-crossing pipeline-SAR ADC in 65nm CMOSJayanth Kuppambatti, Peter R. Kinget. 1-4 [doi]
• Intel Ivy Bridge unveiled - The first commercial tri-gate, high-k, metal-gate CPUDick James. 1-4 [doi]
• ® processor E5 familyMin Huang, Moty Mehalel, Ramesh Arvapalli, Songnian He. 1-4 [doi]
• A 0.1~4GHz receiver and 0.1~6GHz transmitter with reconfigurable 10~100MHz signal bandwidth in 65nm CMOSXinwang Zhang, Yun Yin, Meng Cao, ZhiGang Sun, Ling Fu, Zhaokang Xia, Hongxing Feng, Xing Zhang, Baoyong Chi, Ming Xu, Zhihua Wang. 1-4 [doi]
• Problem of timing mismatch in interleaved ADCsBehzad Razavi. 1-8 [doi]
• A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognitionGuangji He, Takanobu Sugahara, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 1-4 [doi]
• A low-power highly multiplexed parallel PRBS generatorMing-Shuan Chen, Chih-Kong Ken Yang. 1-4 [doi]
• A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADCSi-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. 1-4 [doi]
• Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processorsAyan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar, Chris H. Kim. 1-4 [doi]
• An 8GHz multi-beam spatio-spectral beamforming receiver using an all-passive discrete time analog baseband in 65nm CMOSSatwik A. Patnaik, Sachin Kalia, Bodhisatwa Sadhu, Martin Sturm, Mohammad Elbadry, Ramesh Harjani. 1-4 [doi]
• Analog TechniquesDon Thelen, Xicheng Jiang. 1 [doi]
• Design and manufacturing enablement for three-dimensional (3D) integrated circuits (ICs)Arifur Rahman, Hong Shi, Zhe Li, Dale Ibbotson, Sesh Ramaswami. 1-8 [doi]
• 7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltageToru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada. 1-4 [doi]
• A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOSPierce Chuang, David Li, Manoj Sachdev, Vincent Gaudet. 1-4 [doi]
• A 4.8mW inductorless CMOS frequency divider-by-4 with more than 60% fractional bandwidth up to 70GHzAndrea Ghilioni, Ugo Decanis, Andrea Mazzanti, Francesco Svelto. 1-4 [doi]
• Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuitsHiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. 1-4 [doi]
• A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOST.-W. Chung, T.-C. Huang, S. Chung, M. C. Huang, C. C. Lin, C.-H. Chern, F.-L. Hsueh. 1-4 [doi]
• A 46 μW motion artifact reduction bio-signal sensor with ICA based adaptive DC level control for sleep monitoring systemSunjoo Hong, Seulki Lee, Taehwan Roh, Hoi-Jun Yoo. 1-4 [doi]
• Impedance, filtering and noise in n-phase passive CMOS mixersAlyosha C. Molnar, Caroline Andrews. 1-8 [doi]
• Energy-efficient architecture and enabling technology for advanced SOCsArifur Rahman, Lawrence Clark. 1-2 [doi]
• Phase Change Memory: Scaling and applicationsRakesh Gnana David Jeyasingh, Jiale Liang, Marissa Caldwell, Duygu Kuzum, H.-S. Philip Wong. 1-7 [doi]
• Advanced memory topicsVikas Chandra, Tom Andre. 1 [doi]
• High-speed data convertersEric Naviasky, Mohammad Ranjbar. 1 [doi]
• A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversionSedigheh Hashemi, Behzad Razavi. 1-4 [doi]
• A 695 pW standby power optical wake-up receiver for wireless sensor nodesGyouho Kim, Yoonmyung Lee, Suyoung Bang, Inhee Lee, Yejoong Kim, Dennis Sylvester, David Blaauw. 1-4 [doi]
• A wideband ultra-low-current on-chip ammeterJunjie Lu, Jeremy Holleman. 1-4 [doi]
• Design of high-speed wireline transceivers for backplane communications in 28nm CMOSJafar Savoj, Kenny Hsieh, Parag Upadhyaya, Fu-Tai An, Jay Im, Xuewen Jiang, Jalil Kamali, Kang Wei Lai, Daniel Wu, Elad Alon, Ken Chang. 1-4 [doi]
• A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOSJean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman. 1-4 [doi]
• Statistical aging under dynamic voltage scaling: A logarithmic model approachJyothi Velamala, Ketul Sutaria, Hirofumi Shimizu, Hiromitsu Awano, Takashi Sato, Yu Cao. 1-4 [doi]
• A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-onDustin Dunwell, Anthony Chan Carusone, Jared Zerbe, Brian S. Leibowitz, Barry Daly, John C. Eble. 1-4 [doi]
• A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensationRami A. Abdallah, Naresh R. Shanbhag. 1-4 [doi]
• A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOSLechang Liu, Hiroki Ishikuro, Tadahiro Kuroda. 1-4 [doi]
• 6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOSCagla Cakir, Mudit Bhargava, Ken Mai. 1-4 [doi]
• Amorphous silicon 5 bit flash analog to digital converterAritra Dey, David R. Allee. 1-4 [doi]
• Power managementWilliam McIntyre, Christoph Sandner. 1 [doi]
• Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modulesSteve J. Dillen, Don A. Priore, Aaron Horiuchi, Samuel Naffziger. 1-4 [doi]
• A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOSYue Lu, KwangMo Jung, Yasuo Hidaka, Elad Alon. 1-4 [doi]
• A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct controlHyeok-Ki Hong, Wan Kim, Sun-Jae Park, Michael Choi, Ho-Jin Park, Seung-Tak Ryu. 1-4 [doi]
• A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power modeWei Zhang 0032, Ki Chul Chun, Chris H. Kim. 1-4 [doi]
• PLLs, VCOs, and dividersFa Foster Dai, Howard Luong. 1-2 [doi]
• A hybrid electrical-behavioral modeling approach for pre- and post-silicon electrical validationNagib Hakim, A. Bhaduri, K. Donepudi, S. Bodapati. 1-5 [doi]
• Advanced IC technologies IAlvin Loke, David A. Sunderland. 1 [doi]
• A 65nm CMOS current controlled oscillator with high tuning linearity for wideband polar modulationYiwu Tang, Jianyun Hu, Jongmin Park, Jaehyouk Choi, Lincoln Leung, Chiewcharn Narathong, Kamal Sahota. 1-4 [doi]
• A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOSXiong Zhou, Qiang Li. 1-4 [doi]
• 28-nm HKMG GHz digital sensor for detecting dynamic voltage drops in testing for peak power optimizationMitsuhiko Igarashi, Kan Takeuchi, Yoshio Takazawa, Yasuto Igarashi, Hiroaki Matsushita. 1-4 [doi]
• SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulationEustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David M. Clark, Cameron Patterson, Steve Furber. 1-4 [doi]
• A low-cost audio computer for information dissemination among illiterate people groupsZhiyoong Foo, David Devescery, Mohammad Hassan Ghaed, Inhee Lee, Abishek Madhavan, Youn Sung Park, Aswin Rao, Zach Renner, Nathan Roberts, Aaron Schulman, Vikas Vinay, Michael Wieckowski, Dongmin Yoon, Cliff Schmidt, Thomas Schmid, Prabal Dutta, Peter Chen, David Blaauw. 1-4 [doi]
• A 10.35 mW/GFlop stacked SAR DSP unit using fine-grain partitioned 3D integrationThorlindur Thorolfsson, Steve Lipa, Paul D. Franzon. 1-4 [doi]
• Biomedical and sensorsEmmanuel Quevy, Pedram Mohseni. 1 [doi]
• Fully depleted devices for designers: FDSOI and FinFETsTerence B. Hook. 1-7 [doi]
• Design solutions for 3D integration and signal integrityYu Cao, Siva Mudanai. 1 [doi]
• A 17pJ/bit 915MHz 8PSK/O-QPSK transmitter for high data rate biomedical applicationsMehran M. Izad, Chun-Huat Heng. 1-4 [doi]
• A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB applicationYasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki. 1-4 [doi]
• Non-invasion power monitoring with 120% harvesting energy improvement by maximum power extracting control for high sustainability power meter systemTzu-Chi Huang, Ming-Jhe Du, Yao-Yi Yang, Yu-Huei Lee, Yu-Chai Kang, Ruei-Hong Peng, Ke-Horng Chen. 1-4 [doi]
• A feedback controlled coil driver for transcutaneous power transmissionEdward K. F. Lee. 1-4 [doi]
• A digital phase-locked loop with calibrated coarse and stochastic fine TDCAmer Samarah, Anthony Chan Carusone. 1-4 [doi]
• Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOSMudit Bhargava, Cagla Cakir, Ken Mai. 1-4 [doi]
• True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver exampleJi-Eun Jang, Myeong-Jae Park, Dongyun Lee, Jaeha Kim. 1-4 [doi]
• Characterization of Inverse Temperature Dependence in logic circuitsMinki Cho, Muhammad M. Khellah, Kwanyeob Chae, K. Ahmed, James Tschanz, Saibal Mukhopadhyay. 1-4 [doi]
• A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detectionMyeong-Jae Park, Hanseok Kim, Seuk Son, Jaeha Kim. 1-4 [doi]
• A 180nm CMOS image sensor with on-chip optoelectronic image compressionAlbert Wang, Sriram Sivaramakrishnan, Alyosha Molnar. 1-4 [doi]
• A mixed-mode FPAA SoC for analog-enhanced signal processingCraig Schlottmann, Stephen Nease, Samuel Shapero, Paul E. Hasler. 1-4 [doi]
• Reliability challenges for the continued scaling of IC technologiesAnthony S. Oates. 1-4 [doi]
• A 20 dBm Q-band SiGe Class-E power amplifier with 31% peak PAEKunal Datta, Jonathan Roderick, Hossein Hashemi. 1-4 [doi]
• Linearization of class D amplifiersPio Balmelli, John M. Khoury, Eduardo Viegas, Paulo Santos, Vitor Pereira. 1-4 [doi]
• High-speed wireline transceivers and clockingGerrit den Besten, Shunichi Kaeriyama. 1-2 [doi]
• Extremely thin SOI for system-on-chip applicationsAli Khaki-Firooz, Kangguo Cheng, Qing Liu, Toshiharu Nagumo, Nicolas Loubet, Alexander Reznicek, James Kuss, J. Gimbert, Raghavasimhan Sreenivasan, Maud Vinet, Laurent Grenouillet, Yannick Le Tiec, Romain Wacquez, Z. Ren, J. Cai, Davood Shahrjerdi, Prasanna Kulkarni, Shom Ponoth, Scott Luning, Bruce Doris. 1-4 [doi]
• A compressed-domain processor for seizure detection to simultaneously reduce computation and communication energyMohammed Shoaib, Niraj K. Jha, Naveen Verma. 1-4 [doi]
• A distributed "hybrid" wave oscillator array for millimeter-wave phased-arraysAnna Moroni, Raffaella Genesi, Danilo Manstretta. 1-4 [doi]
• Radio receiver techniquesAlberto Valdes-Garcia, Ramesh Harjani. 1 [doi]
• A digital PLL with two-step closed-locking for multi-mode/multi-band SAW-less transmitterKeisuke Ueda, Toshiya Uozumi, Ryo Endo, Takahiro Nakamura, Tetsuya Heima, Hisayasu Sato. 1-4 [doi]
• A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOSSoon-Kyun Shin, Jacques C. Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer. 1-4 [doi]
• A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOSJean-Olivier Plouchart, Mihai A. T. Sanduleanu, Zeynep Toprak Deniz, Troy J. Beukema, Scott K. Reynolds, Benjamin D. Parker, Michael P. Beakes, José A. Tierno, Daniel J. Friedman. 1-4 [doi]
• 22-nm fully-depleted tri-gate CMOS transistorsChris Auth. 1-6 [doi]
• A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitrationHao Wu, Lan Nan, Sai-Wang Tam, Hsieh-Hung Hsieh, Chewnpu Jou, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang. 1-4 [doi]
• Slew-aware buffer insertion for through-silicon-via-based 3D ICsYoung-Joon Lee, Inki Hong, Sung Kyu Lim. 1-8 [doi]
• Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulatorMichal Rakowski, Julien Ryckaert, Marianna Pantouvaki, Hui Yu, Wim Bogaerts, Kristin De Meyer, Michiel Steyaert, Philippe P. Absil, Joris Van Campenhout. 1-6 [doi]
• A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensationPaul M. Furth, Sri Harsh Pakala, Annajirao Garimella, Chaitanya Mohan. 1-4 [doi]
• Designing reliable analog circuits in an unreliable worldGeorges G. E. Gielen, Elie Maricau, Pieter De Wit. 1-4 [doi]
• An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADCJoseph Hamilton, Shouli Yan, T. R. Viswanathan. 1-4 [doi]
• A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibrationWenbo Liu, Pingli Huang, Yun Chiu. 1-4 [doi]
• A near-threshold, multi-node, wireless body area sensor network powered by RF energy harvestingJiao Cheng, Lingli Xia, Chao Ma, Yong Lian, Xiaoyuan Xu, C. Patrick Yue, Zhiliang Hong, Patrick Yin Chiang. 1-4 [doi]
• CMOS handset power amplifiers: Directions for the futurePeter M. Asbeck, Lawrence E. Larson, Donald Kimball, James F. Buckwalter. 1-6 [doi]
• Data converter techniquesRon Kapusta, Yuji Nakajima. 1 [doi]
• A calibrated pathfinding model for signal integrity analysis on interposerJaemin Kim, Sunyoung Kim, Julien Ryckaert, Mikael Detalle, Nele Van Hoovels, Pol Marchal. 1-4 [doi]
• Lithography and design integration - New paradigm for the technology architecture developmentJongwook Kye, Yuansheng Ma, Lei Yuan, Yunfei Deng, Harry Levinson. 1-4 [doi]
• A 1mJ/frame unified media application processor with a 179.7pJ mixed-mode feature extraction engine for embedded 3D-media contents processingHyo-Eun Kim, Jun-Seok Park, Jae-Sung Yoon, Seok-Hoon Kim, Lee-Sup Kim. 1-4 [doi]
• 2 resonant inductively coupled power transfer for 3D-ICsSangwook Han, David D. Wentzloff. 1-4 [doi]
• A unified model and direct extraction methodologies of various CPWs for CMOS mm-wave applicationsJun Luo, Lei Zhang, Yan Wang. 1-4 [doi]
• A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switchingMasum Hossain, Kambiz Kaviani, Barry Daly, Makarand Shirasgaonkar, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Brian Tsang, John C. Eble, Jared Zerbe. 1-4 [doi]
• Power delivery: Droop, jitter, test and debug story (Tutorial)Mike Li, Manoj Sachdev. 1 [doi]
• Present and future applications of Silicon Carbide devices and circuitsCarl-Mikael Zetterling. 1-8 [doi]
• A custom processor for node and power management of a battery-less body sensor node in 130nm CMOSYousef Shakhsheer, Yanqing Zhang, Brian P. Otis, Benton H. Calhoun. 1-4 [doi]
• A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOSArijit Raychowdhury, Carlos Tokunaga, Willem Beltman, Michael Deisher, James Tschanz, Vivek De. 1-4 [doi]
• FEC-based 4 Gb/s backplane transceiver in 90nm CMOSAdam C. Faust, Rajan Narasimha, Karan S. Bhatia, Ankit Srivastava, Chhay Kong, Hyeon-Min Bae, Elyse Rosenbaum, Naresh R. Shanbhag. 1-4 [doi]
• RMS jitter 1.5mW divider-less FBAR ADPLL in 65nm CMOSJulie R. Hu, Richard C. Ruby, Brian P. Otis. 1-4 [doi]
• Advances in 3D design and optimizationSteven J. E. Wilton, Visvesh Sathe. 1 [doi]