Yasunobu Nakase - researchr alias

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Viewing Publication 1 - 13 from 13

2014

2013

2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer IntegrationYasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu. jssc, 48(8):1933-1942, 2013. [doi]

On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT ModesYasunobu Nakase, Yasuhiro Ido, Tsukasa Oishi, Toru Shimizu. ieicet, 96-C(11):1420-1427, 2013. [doi]

2012

2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integrationYasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu. cicc 2012: 1-4 [doi]

2011

0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computersYasunobu Nakase, Shinichi Hirose, Toru Goda, Kehui Hu, Hiroshi Onoda, Yasuhiro Ido, Hiroyuki Kondo, Wei Kong, Wei Zhang, Tsukasa Oishi, Shintaro Mori, Toru Shimizu. asscc 2011: 21-24 [doi]

2001

A 600-MHz 54/spl times/54-bit multiplier with rectangular-styled Wallace treeNiichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba. jssc, 36(2):249-257, 2001. [doi]

1999

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interfaceYasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada. jssc, 34(4):494-501, 1999. [doi]

1997

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi. jssc, 32(2):292, 1997. [doi]

Authors ReplyHiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko. jssc, 32(2):293, 1997. [doi]

1996

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architectureHiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko. jssc, 31(6):773-783, 1996. [doi]

1995

A BiCMOS wired-OR logicYasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko. jssc, 30(6):622-628, June 1995. [doi]

1993

A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary ArchitectureHiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara. iccd 1993: 202-205

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