Michihiro Yamada - researchr alias

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Viewing Publication 1 - 20 from 20

2021

Best Security Measures to Reduce Cyber-Incident and Data Breach RisksHiroaki Kikuchi, Michihiro Yamada, Kazuki Ikegami, Koji Inui. esorics 2022: 3-19 [doi]

2019

Development of a Cyber Incident Information CrawlerKazuki Ikegami, Michihiro Yamada, Hiroaki Kikuchi, Koji Inui. imis 2020: 447-455 [doi]

Mathematical Model to Estimate Loss by Cyber Incident in JapanMichihiro Yamada, Hiroaki Kikuchi, Naoki Matsuyama, Koji Inui. icissp 2019: 353-360 [doi]

2018

Evaluation and Development of Onomatopoeia CAPTCHAsMichihiro Yamada, Riko Shigeno, Hiroaki Kikuchi, Maki Sakamoto. PST 2018: 1-2 [doi]

2017

How Much is Risk Increased by Sharing Credential in Group?Hiroaki Kikuchi, Koichi Niihara, Michihiro Yamada. STM 2017: 103-117 [doi]

Sharing or Non-sharing Credentials: A Study of What Motivates People to Be Malicious InsidersKoichi Niihara, Michihiro Yamada, Hiroaki Kikuchi. hci 2017: 353-365 [doi]

Decision Tree Analysis on Environmental Factors of Insider ThreatsMichihiro Yamada, Koichi Niihara, Hiroaki Kikuchi. hci 2017: 658-662 [doi]

2001

Design methodology of embedded DRAM with virtual-socket architectureTadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara. jssc, 36(1):46-54, 2001. [doi]

1999

1998

1997

High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI'sTakahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada. jssc, 32(3):477-482, 1997. [doi]

1992

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structureTadato Yamagata, Masaaki Mihara, Takeshi Hamamoto, Yasumitsu Murai, Toshifumi Kobayashi, Michihiro Yamada, Hideyuki Ozaki. jssc, 27(12):1927-1933, December 1992. [doi]

1991

1990

Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAMHiroshi Miyamoto, Tadato Yamagata, Shigeru Mori, Tetsuya Aono, Ikuo Ogoh, Michihiro Yamada. jssc, 25(2):525-530, April 1990. [doi]

1989

A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose registerKazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano. jssc, 24(5):1184-1190, October 1989. [doi]

1985

Test Pattern Considerations for Fault Tolerant High Density DRAMHiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano. itc 1985: 451-455

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