Shimpei Kayano - researchr alias

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Viewing Publication 1 - 6 from 6

1991

A self-learning neural network chip with 125 neurons and 10 K self-organization synapsesYutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Harufusa Kondoh, Shimpei Kayano. jssc, 26(4):607-611, April 1991. [doi]

A 5-ns GaAs 16-kb SRAMShuichi Matsue, Hiroshi Makino, Minoru Noda, Hirofumi Nakano, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano. jssc, 26(10):1399-1406, October 1991. [doi]

A 45-ns 64-Mb DRAM with a merged match-line test architectureShigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano. jssc, 26(11):1486-1492, November 1991. [doi]

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancyAtsushi Ohba, Shigeki Ohbayashi, Toru Shiomi, Satoshi Takano, Kenji Anami, Hiroki Honda, Yoshiyuki Ishigaki, Masahiro Hatanaka, Shigeo Nagao, Shimpei Kayano. jssc, 26(4):507-512, April 1991. [doi]

1990

A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperatureHiroshi Makino, Shuichi Matsue, Minoru Noda, Noriyuki Tanino, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano. jssc, 25(5):1232-1238, October 1990. [doi]

1989

Improvement of soft-error rate in MOS SRAMsShuji Murakami, Katsuki Ichinose, Kenji Anami, Shimpei Kayano. jssc, 24(4):869-873, August 1989. [doi]

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