Kenji Anami - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 13 from 13

2005

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled RefreshHideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara. ieicet, 88-C(4):622-629, 2005. [doi]

1993

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architectureToru Shiomi, Tomohisa Wada, Shigeki Ohbayashi, Atsushi Ohba, Hiroki Honda, Yoshiyuki Ishigaki, Shiro Hine, Kenji Anami, Kimio Suzuki, Tadashi Sumi. jssc, 28(12):1362-1369, December 1993. [doi]

A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM'sMotomu Ukita, Shuji Murakami, Tadato Yamagata, Hirotada Kuriyama, Yasumasa Nishimura, Kenji Anami. jssc, 28(11):1114-1118, November 1993. [doi]

1991

An 8 ns 4 Mb serial access memoryHirotada Kuriyama, Toshihiko Hirose, Shuji Murakami, Tomohisa Wada, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami. jssc, 26(4):502-506, April 1991. [doi]

A 21-mW 4-Mb CMOS SRAM for battery operationShuji Murakami, Kore-aki Fujita, Motomu Ukita, Kazuhito Tsutsumi, Yasuo Inoue, Osamu Sakamoto, Motoi Ashida, Yasumasa Nishimura, Yoshio Kohno, Tadashi Nishimura, Kenji Anami. jssc, 26(11):1563-1570, November 1991. [doi]

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancyAtsushi Ohba, Shigeki Ohbayashi, Toru Shiomi, Satoshi Takano, Kenji Anami, Hiroki Honda, Yoshiyuki Ishigaki, Masahiro Hatanaka, Shigeo Nagao, Shimpei Kayano. jssc, 26(4):507-512, April 1991. [doi]

Variable bit organization as a new test function for standard memoriesTomohisa Wada, Masanao Eino, Motomu Ukita, Kenji Anami. jssc, 26(1):51-54, January 1991. [doi]

1990

A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architectureToshihiko Hirose, Hirotada Kuriyama, Shuji Murakami, Kojiro Yuzuriha, Takao Mukai, Kazuhito Tsutsumi, Yasumasa Nishimura, Yoshio Kohno, Kenji Anami. jssc, 25(5):1068-1074, October 1990. [doi]

Simple noise model and low-noise data-output buffer for ultrahigh-speed memoriesTomohisa Wada, Masanao Eino, Kenji Anami. jssc, 25(6):1586-1588, December 1990. [doi]

1989

Improvement of soft-error rate in MOS SRAMsShuji Murakami, Katsuki Ichinose, Kenji Anami, Shimpei Kayano. jssc, 24(4):869-873, August 1989. [doi]

1988

A macro analysis of soft errors in static RAMsYasunobu Nakase, Kenji Anami, Tohru Shiomi, Atsushi Ohba, Shinpei Kayano. jssc, 23(2):604-605, April 1988. [doi]

Sign in or sign up to see more results.

runs on WebDSL